git.zerfleddert.de Git - proxmark3-svn/blobdiff

#include "string.h"

#include "lfdemod.h"

#include "lfsampling.h"

#include "string.h"

#include "lfdemod.h"

#include "lfsampling.h"

-#include "usb_cdc.h" //test

+#include "protocols.h"

+#include "usb_cdc.h" // for usb_poll_validate_length

/**

* Function to do a modulation and then get samples.

/**

* Function to do a modulation and then get samples.

* @param period_1

* @param command

*/

* @param period_1

* @param command

*/

-void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1, uint8_t *command)

+void ModThenAcquireRawAdcSamples125k(uint32_t delay_off, uint32_t period_0, uint32_t period_1, uint8_t *command)

{

int divisor_used = 95; // 125 KHz

{

int divisor_used = 95; // 125 KHz

sample_config sc = { 0,0,1, divisor_used, 0};

setSamplingConfig(&sc);

sample_config sc = { 0,0,1, divisor_used, 0};

setSamplingConfig(&sc);

+ //clear read buffer

+ BigBuf_Clear_keep_EM();

/* Make sure the tag is reset */

FpgaDownloadAndGo(FPGA_BITSTREAM_LF);

/* Make sure the tag is reset */

FpgaDownloadAndGo(FPGA_BITSTREAM_LF);

DoAcquisition_config(false);

}

DoAcquisition_config(false);

}

-

/* blank r/w tag data stream

...0000000000000000 01111111

1010101010101010101010101010101010101010101010101010101010101010

/* blank r/w tag data stream

...0000000000000000 01111111

1010101010101010101010101010101010101010101010101010101010101010

}

-

void WriteTIbyte(uint8_t b)

{

int i = 0;

void WriteTIbyte(uint8_t b)

{

int i = 0;

// clear buffer

uint32_t *BigBuf = (uint32_t *)BigBuf_get_addr();

// clear buffer

uint32_t *BigBuf = (uint32_t *)BigBuf_get_addr();

- memset(BigBuf,0,BigBuf_max_traceLen()/sizeof(uint32_t));

+ BigBuf_Clear_ext(false);

// Set up the synchronous serial port

AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;

// Set up the synchronous serial port

AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;

}

-

// arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc

// if crc provided, it will be written with the data verbatim (even if bogus)

// if not provided a valid crc will be computed from the data and written.

void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)

{

// arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc

// if crc provided, it will be written with the data verbatim (even if bogus)

// if not provided a valid crc will be computed from the data and written.

void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)

{

-

FpgaDownloadAndGo(FPGA_BITSTREAM_LF);

if(crc == 0) {

crc = update_crc16(crc, (idlo)&0xff);

FpgaDownloadAndGo(FPGA_BITSTREAM_LF);

if(crc == 0) {

crc = update_crc16(crc, (idlo)&0xff);

AcquireTiType();

FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);

AcquireTiType();

FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);

- DbpString("Now use tiread to check");

+ DbpString("Now use `lf ti read` to check");

}

void SimulateTagLowFrequency(int period, int gap, int ledcontrol)

}

void SimulateTagLowFrequency(int period, int gap, int ledcontrol)

AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;

AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;

AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;

AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;

- #define SHORT_COIL() LOW(GPIO_SSC_DOUT)

- #define OPEN_COIL() HIGH(GPIO_SSC_DOUT)

+ #define SHORT_COIL() LOW(GPIO_SSC_DOUT)

+ #define OPEN_COIL() HIGH(GPIO_SSC_DOUT)

i = 0;

for(;;) {

//wait until SSC_CLK goes HIGH

while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {

if(BUTTON_PRESS() || (usb_poll_validate_length() )) {

i = 0;

for(;;) {

//wait until SSC_CLK goes HIGH

while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {

if(BUTTON_PRESS() || (usb_poll_validate_length() )) {

+ FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);

DbpString("Stopped");

return;

}

DbpString("Stopped");

return;

}

LED_D_OFF();

//wait until SSC_CLK goes LOW

while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {

LED_D_OFF();

//wait until SSC_CLK goes LOW

while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {

- if(BUTTON_PRESS()) {

+ if(BUTTON_PRESS() || (usb_poll_validate_length() )) {

DbpString("Stopped");

+ FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);

return;

}

WDT_HIT();

return;

}

WDT_HIT();

SpinDelayUs(gap);

}

SpinDelayUs(gap);

}

+

}

memset(dest+(*n), c ^ *phase, clock);

*phase ^= 1;

}

memset(dest+(*n), c ^ *phase, clock);

*phase ^= 1;

}

+ *n += clock;

+}

+static void stAskSimBit(int *n, uint8_t clock) {

+ uint8_t *dest = BigBuf_get_addr();

+ uint8_t halfClk = clock/2;

+ //ST = .5 high .5 low 1.5 high .5 low 1 high

+ memset(dest+(*n), 1, halfClk);

+ memset(dest+(*n) + halfClk, 0, halfClk);

+ memset(dest+(*n) + clock, 1, clock + halfClk);

+ memset(dest+(*n) + clock*2 + halfClk, 0, halfClk);

+ memset(dest+(*n) + clock*3, 1, clock);

+ *n += clock*4;

}

// args clock, ask/man or askraw, invert, transmission separator

}

// args clock, ask/man or askraw, invert, transmission separator

for (i=0; i<size; i++){

biphaseSimBit(BitStream[i]^invert, &n, clk, &phase);

}

for (i=0; i<size; i++){

biphaseSimBit(BitStream[i]^invert, &n, clk, &phase);

}

- if (BitStream[0]==BitStream[size-1]){ //run a second set inverted to keep phase in check

+ if (phase==1) { //run a second set inverted to keep phase in check

for (i=0; i<size; i++){

biphaseSimBit(BitStream[i]^invert, &n, clk, &phase);

}

for (i=0; i<size; i++){

biphaseSimBit(BitStream[i]^invert, &n, clk, &phase);

}

for (i=0; i<size; i++){

askSimBit(BitStream[i]^invert, &n, clk, encoding);

}

for (i=0; i<size; i++){

askSimBit(BitStream[i]^invert, &n, clk, encoding);

}

- if (encoding==0 && BitStream[0]==BitStream[size-1]){ //run a second set inverted (for biphase phase)

+ if (encoding==0 && BitStream[0]==BitStream[size-1]){ //run a second set inverted (for ask/raw || biphase phase)

for (i=0; i<size; i++){

askSimBit(BitStream[i]^invert^1, &n, clk, encoding);

}

for (i=0; i<size; i++){

askSimBit(BitStream[i]^invert^1, &n, clk, encoding);

}

-

- if (separator==1) Dbprintf("sorry but separator option not yet available");

+ if (separator==1 && encoding == 1)

+ stAskSimBit(&n, clk);

+ else if (separator==1)

+ Dbprintf("sorry but separator option not yet available");

Dbprintf("Simulating with clk: %d, invert: %d, encoding: %d, separator: %d, n: %d",clk, invert, encoding, separator, n);

//DEBUG

Dbprintf("Simulating with clk: %d, invert: %d, encoding: %d, separator: %d, n: %d",clk, invert, encoding, separator, n);

//DEBUG

//Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);

//i+=16;

//Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);

//i+=16;

//Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);

-

- if (ledcontrol)

- LED_A_ON();

+ if (ledcontrol) LED_A_ON();

SimulateTagLowFrequency(n, 0, ledcontrol);

-

- if (ledcontrol)

- LED_A_OFF();

+ if (ledcontrol) LED_A_OFF();

}

//carrier can be 2,4 or 8

}

//carrier can be 2,4 or 8

//i+=16;

//Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);

//i+=16;

//Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);

- if (ledcontrol)

- LED_A_ON();

+ if (ledcontrol) LED_A_ON();

SimulateTagLowFrequency(n, 0, ledcontrol);

-

- if (ledcontrol)

- LED_A_OFF();

+ if (ledcontrol) LED_A_OFF();

}

// loop to get raw HID waveform then FSK demodulate the TAG ID from it

}

// loop to get raw HID waveform then FSK demodulate the TAG ID from it

// Configure to go in 125Khz listen mode

LFSetupFPGAForADC(95, true);

// Configure to go in 125Khz listen mode

LFSetupFPGAForADC(95, true);

+ //clear read buffer

+ BigBuf_Clear_keep_EM();

+

while(!BUTTON_PRESS() && !usb_poll_validate_length()) {

WDT_HIT();

while(!BUTTON_PRESS() && !usb_poll_validate_length()) {

WDT_HIT();

if (ledcontrol) LED_A_OFF();

*high = hi;

*low = lo;

if (ledcontrol) LED_A_OFF();

*high = hi;

*low = lo;

- return;

+ break;

}

// reset

}

hi2 = hi = lo = idx = 0;

WDT_HIT();

}

// reset

}

hi2 = hi = lo = idx = 0;

WDT_HIT();

}

+

+ FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);

DbpString("Stopped");

if (ledcontrol) LED_A_OFF();

}

DbpString("Stopped");

if (ledcontrol) LED_A_OFF();

}

void CmdAWIDdemodFSK(int findone, int *high, int *low, int ledcontrol)

{

uint8_t *dest = BigBuf_get_addr();

void CmdAWIDdemodFSK(int findone, int *high, int *low, int ledcontrol)

{

uint8_t *dest = BigBuf_get_addr();

- //const size_t sizeOfBigBuff = BigBuf_max_traceLen();

size_t size;

int idx=0;

size_t size;

int idx=0;

+ //clear read buffer

+ BigBuf_Clear_keep_EM();

// Configure to go in 125Khz listen mode

LFSetupFPGAForADC(95, true);

// Configure to go in 125Khz listen mode

LFSetupFPGAForADC(95, true);

DoAcquisition_default(-1,true);

// FSK demodulator

DoAcquisition_default(-1,true);

// FSK demodulator

- //size = sizeOfBigBuff; //variable size will change after demod so re initialize it before use

size = 50*128*2; //big enough to catch 2 sequences of largest format

idx = AWIDdemodFSK(dest, &size);

size = 50*128*2; //big enough to catch 2 sequences of largest format

idx = AWIDdemodFSK(dest, &size);

- if (idx>0 && size==96){

- // Index map

- // 0 10 20 30 40 50 60

- // | | | | | | |

- // 01234567 890 1 234 5 678 9 012 3 456 7 890 1 234 5 678 9 012 3 456 7 890 1 234 5 678 9 012 3 - to 96

- // -----------------------------------------------------------------------------

- // 00000001 000 1 110 1 101 1 011 1 101 1 010 0 000 1 000 1 010 0 001 0 110 1 100 0 000 1 000 1

- // premable bbb o bbb o bbw o fff o fff o ffc o ccc o ccc o ccc o ccc o ccc o wxx o xxx o xxx o - to 96

- // |---26 bit---| |-----117----||-------------142-------------|

- // b = format bit len, o = odd parity of last 3 bits

- // f = facility code, c = card number

- // w = wiegand parity

- // (26 bit format shown)

-

- //get raw ID before removing parities

- uint32_t rawLo = bytebits_to_byte(dest+idx+64,32);

- uint32_t rawHi = bytebits_to_byte(dest+idx+32,32);

- uint32_t rawHi2 = bytebits_to_byte(dest+idx,32);

-

- size = removeParity(dest, idx+8, 4, 1, 88);

- // ok valid card found!

-

- // Index map

- // 0 10 20 30 40 50 60

- // | | | | | | |

- // 01234567 8 90123456 7890123456789012 3 456789012345678901234567890123456

- // -----------------------------------------------------------------------------

- // 00011010 1 01110101 0000000010001110 1 000000000000000000000000000000000

- // bbbbbbbb w ffffffff cccccccccccccccc w xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx

- // |26 bit| |-117--| |-----142------|

- // b = format bit len, o = odd parity of last 3 bits

- // f = facility code, c = card number

- // w = wiegand parity

- // (26 bit format shown)

-

- uint32_t fc = 0;

- uint32_t cardnum = 0;

- uint32_t code1 = 0;

- uint32_t code2 = 0;

- uint8_t fmtLen = bytebits_to_byte(dest,8);

- if (fmtLen==26){

- fc = bytebits_to_byte(dest+9, 8);

- cardnum = bytebits_to_byte(dest+17, 16);

- code1 = bytebits_to_byte(dest+8,fmtLen);

- Dbprintf("AWID Found - BitLength: %d, FC: %d, Card: %d - Wiegand: %x, Raw: %08x%08x%08x", fmtLen, fc, cardnum, code1, rawHi2, rawHi, rawLo);

- } else {

- cardnum = bytebits_to_byte(dest+8+(fmtLen-17), 16);

- if (fmtLen>32){

- code1 = bytebits_to_byte(dest+8,fmtLen-32);

- code2 = bytebits_to_byte(dest+8+(fmtLen-32),32);

- Dbprintf("AWID Found - BitLength: %d -unknown BitLength- (%d) - Wiegand: %x%08x, Raw: %08x%08x%08x", fmtLen, cardnum, code1, code2, rawHi2, rawHi, rawLo);

- } else{

- code1 = bytebits_to_byte(dest+8,fmtLen);

- Dbprintf("AWID Found - BitLength: %d -unknown BitLength- (%d) - Wiegand: %x, Raw: %08x%08x%08x", fmtLen, cardnum, code1, rawHi2, rawHi, rawLo);

- }

- if (findone){

- if (ledcontrol) LED_A_OFF();

- return;

+ if (idx<=0 || size!=96) continue;

+ // Index map

+ // 0 10 20 30 40 50 60

+ // | | | | | | |

+ // 01234567 890 1 234 5 678 9 012 3 456 7 890 1 234 5 678 9 012 3 456 7 890 1 234 5 678 9 012 3 - to 96

+ // -----------------------------------------------------------------------------

+ // 00000001 000 1 110 1 101 1 011 1 101 1 010 0 000 1 000 1 010 0 001 0 110 1 100 0 000 1 000 1

+ // premable bbb o bbb o bbw o fff o fff o ffc o ccc o ccc o ccc o ccc o ccc o wxx o xxx o xxx o - to 96

+ // |---26 bit---| |-----117----||-------------142-------------|

+ // b = format bit len, o = odd parity of last 3 bits

+ // f = facility code, c = card number

+ // w = wiegand parity

+ // (26 bit format shown)

+

+ //get raw ID before removing parities

+ uint32_t rawLo = bytebits_to_byte(dest+idx+64,32);

+ uint32_t rawHi = bytebits_to_byte(dest+idx+32,32);

+ uint32_t rawHi2 = bytebits_to_byte(dest+idx,32);

+

+ size = removeParity(dest, idx+8, 4, 1, 88);

+ if (size != 66) continue;

+ // ok valid card found!

+

+ // Index map

+ // 0 10 20 30 40 50 60

+ // | | | | | | |

+ // 01234567 8 90123456 7890123456789012 3 456789012345678901234567890123456

+ // -----------------------------------------------------------------------------

+ // 00011010 1 01110101 0000000010001110 1 000000000000000000000000000000000

+ // bbbbbbbb w ffffffff cccccccccccccccc w xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx

+ // |26 bit| |-117--| |-----142------|

+ // b = format bit len, o = odd parity of last 3 bits

+ // f = facility code, c = card number

+ // w = wiegand parity

+ // (26 bit format shown)

+

+ uint32_t fc = 0;

+ uint32_t cardnum = 0;

+ uint32_t code1 = 0;

+ uint32_t code2 = 0;

+ uint8_t fmtLen = bytebits_to_byte(dest,8);

+ if (fmtLen==26){

+ fc = bytebits_to_byte(dest+9, 8);

+ cardnum = bytebits_to_byte(dest+17, 16);

+ code1 = bytebits_to_byte(dest+8,fmtLen);

+ Dbprintf("AWID Found - BitLength: %d, FC: %d, Card: %d - Wiegand: %x, Raw: %08x%08x%08x", fmtLen, fc, cardnum, code1, rawHi2, rawHi, rawLo);

+ } else {

+ cardnum = bytebits_to_byte(dest+8+(fmtLen-17), 16);

+ if (fmtLen>32){

+ code1 = bytebits_to_byte(dest+8,fmtLen-32);

+ code2 = bytebits_to_byte(dest+8+(fmtLen-32),32);

+ Dbprintf("AWID Found - BitLength: %d -unknown BitLength- (%d) - Wiegand: %x%08x, Raw: %08x%08x%08x", fmtLen, cardnum, code1, code2, rawHi2, rawHi, rawLo);

+ } else{

+ code1 = bytebits_to_byte(dest+8,fmtLen);

+ Dbprintf("AWID Found - BitLength: %d -unknown BitLength- (%d) - Wiegand: %x, Raw: %08x%08x%08x", fmtLen, cardnum, code1, rawHi2, rawHi, rawLo);

}

- // reset

}

+ if (findone){

+ if (ledcontrol) LED_A_OFF();

+ break;

+ }

+ // reset

idx = 0;

WDT_HIT();

}

idx = 0;

WDT_HIT();

}

+ FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);

DbpString("Stopped");

if (ledcontrol) LED_A_OFF();

}

DbpString("Stopped");

if (ledcontrol) LED_A_OFF();

}

int clk=0, invert=0, errCnt=0, maxErr=20;

uint32_t hi=0;

uint64_t lo=0;

int clk=0, invert=0, errCnt=0, maxErr=20;

uint32_t hi=0;

uint64_t lo=0;

+ //clear read buffer

+ BigBuf_Clear_keep_EM();

// Configure to go in 125Khz listen mode

LFSetupFPGAForADC(95, true);

// Configure to go in 125Khz listen mode

LFSetupFPGAForADC(95, true);

if (ledcontrol) LED_A_OFF();

*high=lo>>32;

*low=lo & 0xFFFFFFFF;

if (ledcontrol) LED_A_OFF();

*high=lo>>32;

*low=lo & 0xFFFFFFFF;

- return;

+ break;

}

WDT_HIT();

hi = lo = size = idx = 0;

clk = invert = errCnt = 0;

}

WDT_HIT();

hi = lo = size = idx = 0;

clk = invert = errCnt = 0;

}

+ FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);

DbpString("Stopped");

if (ledcontrol) LED_A_OFF();

}

DbpString("Stopped");

if (ledcontrol) LED_A_OFF();

}

uint8_t version=0;

uint8_t facilitycode=0;

uint16_t number=0;

uint8_t version=0;

uint8_t facilitycode=0;

uint16_t number=0;

+ //clear read buffer

+ BigBuf_Clear_keep_EM();

// Configure to go in 125Khz listen mode

LFSetupFPGAForADC(95, true);

// Configure to go in 125Khz listen mode

LFSetupFPGAForADC(95, true);

//LED_A_OFF();

*high=code;

*low=code2;

//LED_A_OFF();

*high=code;

*low=code2;

- return;

+ break;

}

code=code2=0;

version=facilitycode=0;

}

code=code2=0;

version=facilitycode=0;

WDT_HIT();

}

WDT_HIT();

}

+ FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);

DbpString("Stopped");

if (ledcontrol) LED_A_OFF();

}

/*------------------------------

DbpString("Stopped");

if (ledcontrol) LED_A_OFF();

}

/*------------------------------

- * T5555/T5557/T5567 routines

+ * T5555/T5557/T5567/T5577 routines

*------------------------------

- */

-

-/* T55x7 configuration register definitions */

-#define T55x7_POR_DELAY 0x00000001

-#define T55x7_ST_TERMINATOR 0x00000008

-#define T55x7_PWD 0x00000010

-#define T55x7_MAXBLOCK_SHIFT 5

-#define T55x7_AOR 0x00000200

-#define T55x7_PSKCF_RF_2 0

-#define T55x7_PSKCF_RF_4 0x00000400

-#define T55x7_PSKCF_RF_8 0x00000800

-#define T55x7_MODULATION_DIRECT 0

-#define T55x7_MODULATION_PSK1 0x00001000

-#define T55x7_MODULATION_PSK2 0x00002000

-#define T55x7_MODULATION_PSK3 0x00003000

-#define T55x7_MODULATION_FSK1 0x00004000

-#define T55x7_MODULATION_FSK2 0x00005000

-#define T55x7_MODULATION_FSK1a 0x00006000

-#define T55x7_MODULATION_FSK2a 0x00007000

-#define T55x7_MODULATION_MANCHESTER 0x00008000

-#define T55x7_MODULATION_BIPHASE 0x00010000

-#define T55x7_MODULATION_DIPHASE 0x00018000

-#define T55x7_BITRATE_RF_8 0

-#define T55x7_BITRATE_RF_16 0x00040000

-#define T55x7_BITRATE_RF_32 0x00080000

-#define T55x7_BITRATE_RF_40 0x000C0000

-#define T55x7_BITRATE_RF_50 0x00100000

-#define T55x7_BITRATE_RF_64 0x00140000

-#define T55x7_BITRATE_RF_100 0x00180000

-#define T55x7_BITRATE_RF_128 0x001C0000

-

-/* T5555 (Q5) configuration register definitions */

-#define T5555_ST_TERMINATOR 0x00000001

-#define T5555_MAXBLOCK_SHIFT 0x00000001

-#define T5555_MODULATION_MANCHESTER 0

-#define T5555_MODULATION_PSK1 0x00000010

-#define T5555_MODULATION_PSK2 0x00000020

-#define T5555_MODULATION_PSK3 0x00000030

-#define T5555_MODULATION_FSK1 0x00000040

-#define T5555_MODULATION_FSK2 0x00000050

-#define T5555_MODULATION_BIPHASE 0x00000060

-#define T5555_MODULATION_DIRECT 0x00000070

-#define T5555_INVERT_OUTPUT 0x00000080

-#define T5555_PSK_RF_2 0

-#define T5555_PSK_RF_4 0x00000100

-#define T5555_PSK_RF_8 0x00000200

-#define T5555_USE_PWD 0x00000400

-#define T5555_USE_AOR 0x00000800

-#define T5555_BITRATE_SHIFT 12

-#define T5555_FAST_WRITE 0x00004000

-#define T5555_PAGE_SELECT 0x00008000

-

-/*

- * Relevant times in microsecond

+ * NOTE: T55x7/T5555 configuration register definitions moved to protocols.h

+ *

+ * Relevant communication times in microsecond

* To compensate antenna falling times shorten the write times

* and enlarge the gap ones.

* To compensate antenna falling times shorten the write times

* and enlarge the gap ones.

+ * Q5 tags seems to have issues when these values changes.

*/

#define START_GAP 31*8 // was 250 // SPEC: 1*8 to 50*8 - typ 15*8 (or 15fc)

#define WRITE_GAP 20*8 // was 160 // SPEC: 1*8 to 20*8 - typ 10*8 (or 10fc)

#define WRITE_0 18*8 // was 144 // SPEC: 16*8 to 32*8 - typ 24*8 (or 24fc)

#define WRITE_1 50*8 // was 400 // SPEC: 48*8 to 64*8 - typ 56*8 (or 56fc) 432 for T55x7; 448 for E5550

*/

#define START_GAP 31*8 // was 250 // SPEC: 1*8 to 50*8 - typ 15*8 (or 15fc)

#define WRITE_GAP 20*8 // was 160 // SPEC: 1*8 to 20*8 - typ 10*8 (or 10fc)

#define WRITE_0 18*8 // was 144 // SPEC: 16*8 to 32*8 - typ 24*8 (or 24fc)

#define WRITE_1 50*8 // was 400 // SPEC: 48*8 to 64*8 - typ 56*8 (or 56fc) 432 for T55x7; 448 for E5550

+#define READ_GAP 15*8

-#define T55xx_SAMPLES_SIZE 12000 // 32 x 32 x 10 (32 bit times numofblock (7), times clock skip..)

-#define T55xx_READ_UPPER_THRESHOLD 128+40 // 50

-#define T55xx_READ_TOL 5

-//#define T55xx_READ_LOWER_THRESHOLD 128-40 //-50

-// Write one bit to card

-void T55xxWriteBit(int bit)

-{

- FpgaDownloadAndGo(FPGA_BITSTREAM_LF);

- FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz

+void TurnReadLFOn(int delay) {

FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);

- if (bit == 0)

- SpinDelayUs(WRITE_0);

+ // Give it a bit of time for the resonant antenna to settle.

+ SpinDelayUs(delay); //155*8 //50*8

+}

+

+// Write one bit to card

+void T55xxWriteBit(int bit) {

+ if (!bit)

+ TurnReadLFOn(WRITE_0);

else

- SpinDelayUs(WRITE_1);

+ TurnReadLFOn(WRITE_1);

FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);

SpinDelayUs(WRITE_GAP);

}

FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);

SpinDelayUs(WRITE_GAP);

}

+// Send T5577 reset command then read stream (see if we can identify the start of the stream)

+void T55xxResetRead(void) {

+ LED_A_ON();

+ //clear buffer now so it does not interfere with timing later

+ BigBuf_Clear_keep_EM();

+

+ // Set up FPGA, 125kHz

+ LFSetupFPGAForADC(95, true);

+

+ // Trigger T55x7 in mode.

+ FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);

+ SpinDelayUs(START_GAP);

+

+ // reset tag - op code 00

+ T55xxWriteBit(0);

+

+ // Turn field on to read the response

+ TurnReadLFOn(READ_GAP);

+

+ // Acquisition

+ doT55x7Acquisition(BigBuf_max_traceLen());

+

+ // Turn the field off

+ FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off

+ cmd_send(CMD_ACK,0,0,0,0,0);

+ LED_A_OFF();

+}

+

// Write one card block in page 0, no lock

-void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMode)

-{

+void T55xxWriteBlockExt(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t arg) {

+ LED_A_ON();

+ bool PwdMode = arg & 0x1;

+ uint8_t Page = (arg & 0x2)>>1;

uint32_t i = 0;

// Set up FPGA, 125kHz

uint32_t i = 0;

// Set up FPGA, 125kHz

- // Wait for config.. (192+8190xPOW)x8 == 67ms

LFSetupFPGAForADC(95, true);

- // Now start writting

+ // Trigger T55x7 in mode.

FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);

SpinDelayUs(START_GAP);

FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);

SpinDelayUs(START_GAP);

- // Opcode

+ // Opcode 10

T55xxWriteBit(1);

- T55xxWriteBit(0); //Page 0

- if (PwdMode == 1){

- // Pwd

+ T55xxWriteBit(Page); //Page 0

+ if (PwdMode){

+ // Send Pwd

for (i = 0x80000000; i != 0; i >>= 1)

T55xxWriteBit(Pwd & i);

}

for (i = 0x80000000; i != 0; i >>= 1)

T55xxWriteBit(Pwd & i);

}

- // Lock bit

+ // Send Lock bit

T55xxWriteBit(0);

- // Data

+ // Send Data

for (i = 0x80000000; i != 0; i >>= 1)

T55xxWriteBit(Data & i);

for (i = 0x80000000; i != 0; i >>= 1)

T55xxWriteBit(Data & i);

- // Block

+ // Send Block number

for (i = 0x04; i != 0; i >>= 1)

T55xxWriteBit(Block & i);

for (i = 0x04; i != 0; i >>= 1)

T55xxWriteBit(Block & i);

- // Now perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,

+ // Perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,

// so wait a little more)

- FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz

- FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);

- SpinDelay(20);

+ TurnReadLFOn(20 * 1000);

+ //could attempt to do a read to confirm write took

+ // as the tag should repeat back the new block

+ // until it is reset, but to confirm it we would

+ // need to know the current block 0 config mode

+

+ // turn field off

FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);

+ LED_A_OFF();

}

-void TurnReadLFOn(){

- FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);

- // Give it a bit of time for the resonant antenna to settle.

- SpinDelayUs(50*8); //155*8

+// Write one card block in page 0, no lock

+void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t arg) {

+ T55xxWriteBlockExt(Data, Block, Pwd, arg);

+ cmd_send(CMD_ACK,0,0,0,0,0);

}

-

-// Read one card block in page 0

-void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)

-{

+// Read one card block in page [page]

+void T55xxReadBlock(uint16_t arg0, uint8_t Block, uint32_t Pwd) {

+ LED_A_ON();

+ bool PwdMode = arg0 & 0x1;

+ uint8_t Page = (arg0 & 0x2) >> 1;

uint32_t i = 0;

- uint8_t *dest = BigBuf_get_addr();

- uint16_t bufferlength = BigBuf_max_traceLen();

- if ( bufferlength > T55xx_SAMPLES_SIZE )

- bufferlength = T55xx_SAMPLES_SIZE;

- Block &= 0x7; //make sure block is at max 7

- // Clear destination buffer before sending the command

- memset(dest, 0x80, bufferlength);

+ bool RegReadMode = (Block == 0xFF);

- // Set up FPGA, 125kHz

- // Wait for config.. (192+8190xPOW)x8 == 67ms

-

- LFSetupFPGAForADC(95, true);

- FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);

+ //clear buffer now so it does not interfere with timing later

+ BigBuf_Clear_ext(false);

- // Connect the A/D to the peak-detected low-frequency path.

- SetAdcMuxFor(GPIO_MUXSEL_LOPKD);

+ //make sure block is at max 7

+ Block &= 0x7;

- // Now set up the SSC to get the ADC samples that are now streaming at us.

- FpgaSetupSsc();

-

- // Give it a bit of time for the resonant antenna to settle.

- //SpinDelayUs(8*200); //192FC

- SpinDelay(50);

+ // Set up FPGA, 125kHz to power up the tag

+ LFSetupFPGAForADC(95, true);

+ // Trigger T55x7 Direct Access Mode with start gap

FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);

SpinDelayUs(START_GAP);

FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);

SpinDelayUs(START_GAP);

- // Opcode

+ // Opcode 1[page]

T55xxWriteBit(1);

- T55xxWriteBit(0); //Page 0

- if (PwdMode == 1){

- // Pwd

+ T55xxWriteBit(Page); //Page 0

+

+ if (PwdMode){

+ // Send Pwd

for (i = 0x80000000; i != 0; i >>= 1)

T55xxWriteBit(Pwd & i);

}

for (i = 0x80000000; i != 0; i >>= 1)

T55xxWriteBit(Pwd & i);

}

- // Lock bit

+ // Send a zero bit separation

T55xxWriteBit(0);

- // Block

- for (i = 0x04; i != 0; i >>= 1)

- T55xxWriteBit(Block & i);

+

+ // Send Block number (if direct access mode)

+ if (!RegReadMode)

+ for (i = 0x04; i != 0; i >>= 1)

+ T55xxWriteBit(Block & i);

// Turn field on to read the response

- TurnReadLFOn();

- // Now do the acquisition

- i = 0;

- bool startFound = false;

- bool highFound = false;

- uint8_t curSample = 0;

- uint8_t firstSample = 0;

- for(;;) {

- if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {

- AT91C_BASE_SSC->SSC_THR = 0x43;

- LED_D_ON();

- }

- if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {

- curSample = (uint8_t)AT91C_BASE_SSC->SSC_RHR;

-

- // find first high sample

- if (!startFound && curSample > T55xx_READ_UPPER_THRESHOLD) {

- if (curSample > firstSample) firstSample = curSample;

- highFound = true;

- } else if (!highFound) {

- continue;

- }

+ TurnReadLFOn(READ_GAP);

- // skip until samples begin to change

- if (startFound || curSample < firstSample-T55xx_READ_TOL){

- if (!startFound) dest[i++] = firstSample;

- startFound = true;

- dest[i++] = curSample;

- LED_D_OFF();

- if (i >= bufferlength) break;

- }

+ // Acquisition

+ doT55x7Acquisition(12000);

- cmd_send(CMD_ACK,0,0,0,0,0);

+ // Turn the field off

FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off

- LED_D_OFF();

+ cmd_send(CMD_ACK,0,0,0,0,0);

+ LED_A_OFF();

}

-// Read card traceability data (page 1)

-void T55xxReadTrace(void){

-

+void T55xxWakeUp(uint32_t Pwd){

+ LED_B_ON();

uint32_t i = 0;

- uint8_t *dest = BigBuf_get_addr();

- uint16_t bufferlength = BigBuf_max_traceLen();

- if ( bufferlength > T55xx_SAMPLES_SIZE )

- bufferlength= T55xx_SAMPLES_SIZE;

-

- // Clear destination buffer before sending the command

- memset(dest, 0x80, bufferlength);

-

- LFSetupFPGAForADC(0, true);

+

+ // Set up FPGA, 125kHz

+ LFSetupFPGAForADC(95, true);

+

+ // Trigger T55x7 Direct Access Mode

FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);

SpinDelayUs(START_GAP);

FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);

SpinDelayUs(START_GAP);

-

- // Opcode

+

+ // Opcode 10

T55xxWriteBit(1);

- T55xxWriteBit(1); //Page 1

+ T55xxWriteBit(0); //Page 0

- // Turn field on to read the response

- TurnReadLFOn();

+ // Send Pwd

+ for (i = 0x80000000; i != 0; i >>= 1)

+ T55xxWriteBit(Pwd & i);

- // Now do the acquisition

- bool startFound = false;// false;

- bool highFound = false;

- uint8_t curSample = 0;

- uint8_t firstSample = 0;

- for(;;) {

- if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {

- AT91C_BASE_SSC->SSC_THR = 0x43;

- LED_D_ON();

- }

- if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {

- curSample = (uint8_t)AT91C_BASE_SSC->SSC_RHR;

-

- // find first high sample

- if (!startFound && curSample > T55xx_READ_UPPER_THRESHOLD) {

- if (curSample > firstSample) firstSample = curSample;

- highFound = true;

- } else if (!highFound) {

- continue;

- }

+ // Turn and leave field on to let the begin repeating transmission

+ TurnReadLFOn(20*1000);

+}

- // skip until samples begin to change

- if (startFound || curSample < firstSample-T55xx_READ_TOL){

- if (!startFound) dest[i++] = firstSample;

- startFound = true;

- dest[i++] = curSample;

- LED_D_OFF();

- if (i >= bufferlength) break;

- }

+/*-------------- Cloning routines -----------*/

- cmd_send(CMD_ACK,0,0,0,0,0);

- FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off

- LED_D_OFF();

+void WriteT55xx(uint32_t *blockdata, uint8_t startblock, uint8_t numblocks) {

+ // write last block first and config block last (if included)

+ for (uint8_t i = numblocks+startblock; i > startblock; i--) {

+ T55xxWriteBlockExt(blockdata[i-1],i-1,0,0);

+ }

}

-/*-------------- Cloning routines -----------*/

// Copy HID id to card and setup block 0 config

-void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT)

-{

- int data1=0, data2=0, data3=0, data4=0, data5=0, data6=0; //up to six blocks for long format

- int last_block = 0;

+void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT) {

+ uint32_t data[] = {0,0,0,0,0,0,0};

+ uint8_t last_block = 0;

- if (longFMT){

+ if (longFMT) {

// Ensure no more than 84 bits supplied

if (hi2>0xFFFFF) {

DbpString("Tags can only have 84 bits.");

// Ensure no more than 84 bits supplied

if (hi2>0xFFFFF) {

DbpString("Tags can only have 84 bits.");

}

// Build the 6 data blocks for supplied 84bit ID

last_block = 6;

}

// Build the 6 data blocks for supplied 84bit ID

last_block = 6;

- data1 = 0x1D96A900; // load preamble (1D) & long format identifier (9E manchester encoded)

- for (int i=0;i<4;i++) {

- if (hi2 & (1<<(19-i)))

- data1 |= (1<<(((3-i)*2)+1)); // 1 -> 10

- else

- data1 |= (1<<((3-i)*2)); // 0 -> 01

- }

-

- data2 = 0;

- for (int i=0;i<16;i++) {

- if (hi2 & (1<<(15-i)))

- data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10

- else

- data2 |= (1<<((15-i)*2)); // 0 -> 01

- }

-

- data3 = 0;

- for (int i=0;i<16;i++) {

- if (hi & (1<<(31-i)))

- data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10

- else

- data3 |= (1<<((15-i)*2)); // 0 -> 01

- }

-

- data4 = 0;

- for (int i=0;i<16;i++) {

- if (hi & (1<<(15-i)))

- data4 |= (1<<(((15-i)*2)+1)); // 1 -> 10

- else

- data4 |= (1<<((15-i)*2)); // 0 -> 01

- }

-

- data5 = 0;

- for (int i=0;i<16;i++) {

- if (lo & (1<<(31-i)))

- data5 |= (1<<(((15-i)*2)+1)); // 1 -> 10

- else

- data5 |= (1<<((15-i)*2)); // 0 -> 01

- }

-

- data6 = 0;

- for (int i=0;i<16;i++) {

- if (lo & (1<<(15-i)))

- data6 |= (1<<(((15-i)*2)+1)); // 1 -> 10

- else

- data6 |= (1<<((15-i)*2)); // 0 -> 01

- }

- else {

+ // load preamble (1D) & long format identifier (9E manchester encoded)

+ data[1] = 0x1D96A900 | (manchesterEncode2Bytes((hi2 >> 16) & 0xF) & 0xFF);

+ // load raw id from hi2, hi, lo to data blocks (manchester encoded)

+ data[2] = manchesterEncode2Bytes(hi2 & 0xFFFF);

+ data[3] = manchesterEncode2Bytes(hi >> 16);

+ data[4] = manchesterEncode2Bytes(hi & 0xFFFF);

+ data[5] = manchesterEncode2Bytes(lo >> 16);

+ data[6] = manchesterEncode2Bytes(lo & 0xFFFF);

+ } else {

// Ensure no more than 44 bits supplied

if (hi>0xFFF) {

DbpString("Tags can only have 44 bits.");

return;

}

// Ensure no more than 44 bits supplied

if (hi>0xFFF) {

DbpString("Tags can only have 44 bits.");

return;

}

-

// Build the 3 data blocks for supplied 44bit ID

last_block = 3;

// Build the 3 data blocks for supplied 44bit ID

last_block = 3;

-

- data1 = 0x1D000000; // load preamble

-

- for (int i=0;i<12;i++) {

- if (hi & (1<<(11-i)))

- data1 |= (1<<(((11-i)*2)+1)); // 1 -> 10

- else

- data1 |= (1<<((11-i)*2)); // 0 -> 01

- }

-

- data2 = 0;

- for (int i=0;i<16;i++) {

- if (lo & (1<<(31-i)))

- data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10

- else

- data2 |= (1<<((15-i)*2)); // 0 -> 01

- }

-

- data3 = 0;

- for (int i=0;i<16;i++) {

- if (lo & (1<<(15-i)))

- data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10

- else

- data3 |= (1<<((15-i)*2)); // 0 -> 01

- }

+ // load preamble

+ data[1] = 0x1D000000 | (manchesterEncode2Bytes(hi) & 0xFFFFFF);

+ data[2] = manchesterEncode2Bytes(lo >> 16);

+ data[3] = manchesterEncode2Bytes(lo & 0xFFFF);

}

+ // load chip config block

+ data[0] = T55x7_BITRATE_RF_50 | T55x7_MODULATION_FSK2a | last_block << T55x7_MAXBLOCK_SHIFT;

+

+ //TODO add selection of chip for Q5 or T55x7

+ // data[0] = (((50-2)/2)<<T5555_BITRATE_SHIFT) | T5555_MODULATION_FSK2 | T5555_INVERT_OUTPUT | last_block << T5555_MAXBLOCK_SHIFT;

LED_D_ON();

// Program the data blocks for supplied ID

// and the block 0 for HID format

LED_D_ON();

// Program the data blocks for supplied ID

// and the block 0 for HID format

- T55xxWriteBlock(data1,1,0,0);

- T55xxWriteBlock(data2,2,0,0);

- T55xxWriteBlock(data3,3,0,0);

-

- if (longFMT) { // if long format there are 6 blocks

- T55xxWriteBlock(data4,4,0,0);

- T55xxWriteBlock(data5,5,0,0);

- T55xxWriteBlock(data6,6,0,0);

- }

-

- // Config for HID (RF/50, FSK2a, Maxblock=3 for short/6 for long)

- T55xxWriteBlock(T55x7_BITRATE_RF_50 |

- T55x7_MODULATION_FSK2a |

- last_block << T55x7_MAXBLOCK_SHIFT,

- 0,0,0);

+ WriteT55xx(data, 0, last_block+1);

LED_D_OFF();

DbpString("DONE!");

}

LED_D_OFF();

DbpString("DONE!");

}

-void CopyIOtoT55x7(uint32_t hi, uint32_t lo, uint8_t longFMT)

-{

- int data1=0, data2=0; //up to six blocks for long format

-

- data1 = hi; // load preamble

- data2 = lo;

+void CopyIOtoT55x7(uint32_t hi, uint32_t lo) {

+ uint32_t data[] = {T55x7_BITRATE_RF_64 | T55x7_MODULATION_FSK2a | (2 << T55x7_MAXBLOCK_SHIFT), hi, lo};

+ //TODO add selection of chip for Q5 or T55x7

+ // data[0] = (((64-2)/2)<<T5555_BITRATE_SHIFT) | T5555_MODULATION_FSK2 | T5555_INVERT_OUTPUT | 2 << T5555_MAXBLOCK_SHIFT;

LED_D_ON();

// Program the data blocks for supplied ID

LED_D_ON();

// Program the data blocks for supplied ID

- // and the block 0 for HID format

- T55xxWriteBlock(data1,1,0,0);

- T55xxWriteBlock(data2,2,0,0);

+ // and the block 0 config

+ WriteT55xx(data, 0, 3);

- //Config Block

- T55xxWriteBlock(0x00147040,0,0,0);

LED_D_OFF();

DbpString("DONE!");

}

LED_D_OFF();

DbpString("DONE!");

}

+// Clone Indala 64-bit tag by UID to T55x7

+void CopyIndala64toT55x7(uint32_t hi, uint32_t lo) {

+ //Program the 2 data blocks for supplied 64bit UID

+ // and the Config for Indala 64 format (RF/32;PSK1 with RF/2;Maxblock=2)

+ uint32_t data[] = { T55x7_BITRATE_RF_32 | T55x7_MODULATION_PSK1 | (2 << T55x7_MAXBLOCK_SHIFT), hi, lo};

+ //TODO add selection of chip for Q5 or T55x7

+ // data[0] = (((32-2)/2)<<T5555_BITRATE_SHIFT) | T5555_MODULATION_PSK1 | 2 << T5555_MAXBLOCK_SHIFT;

+

+ WriteT55xx(data, 0, 3);

+ //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)

+ // T5567WriteBlock(0x603E1042,0);

+ DbpString("DONE!");

+}

+// Clone Indala 224-bit tag by UID to T55x7

+void CopyIndala224toT55x7(uint32_t uid1, uint32_t uid2, uint32_t uid3, uint32_t uid4, uint32_t uid5, uint32_t uid6, uint32_t uid7) {

+ //Program the 7 data blocks for supplied 224bit UID

+ uint32_t data[] = {0, uid1, uid2, uid3, uid4, uid5, uid6, uid7};

+ // and the block 0 for Indala224 format

+ //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7)

+ data[0] = T55x7_BITRATE_RF_32 | T55x7_MODULATION_PSK1 | (7 << T55x7_MAXBLOCK_SHIFT);

+ //TODO add selection of chip for Q5 or T55x7

+ // data[0] = (((32-2)>>1)<<T5555_BITRATE_SHIFT) | T5555_MODULATION_PSK1 | 7 << T5555_MAXBLOCK_SHIFT;

+ WriteT55xx(data, 0, 8);

+ //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)

+ // T5567WriteBlock(0x603E10E2,0);

+ DbpString("DONE!");

+}

+// clone viking tag to T55xx

+void CopyVikingtoT55xx(uint32_t block1, uint32_t block2, uint8_t Q5) {

+ uint32_t data[] = {T55x7_BITRATE_RF_32 | T55x7_MODULATION_MANCHESTER | (2 << T55x7_MAXBLOCK_SHIFT), block1, block2};

+ if (Q5) data[0] = ( ((32-2)>>1) << T5555_BITRATE_SHIFT) | T5555_MODULATION_MANCHESTER | 2 << T5555_MAXBLOCK_SHIFT;

+ // Program the data blocks for supplied ID and the block 0 config

+ WriteT55xx(data, 0, 3);

+ LED_D_OFF();

+ cmd_send(CMD_ACK,0,0,0,0,0);

+}

+

// Define 9bit header for EM410x tags

-#define EM410X_HEADER 0x1FF

+#define EM410X_HEADER 0x1FF

#define EM410X_ID_LENGTH 40

-void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo)

-{

+void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo) {

int i, id_bit;

uint64_t id = EM410X_HEADER;

uint64_t rev_id = 0; // reversed ID

int i, id_bit;

uint64_t id = EM410X_HEADER;

uint64_t rev_id = 0; // reversed ID

LED_D_ON();

// Write EM410x ID

LED_D_ON();

// Write EM410x ID

- T55xxWriteBlock((uint32_t)(id >> 32), 1, 0, 0);

- T55xxWriteBlock((uint32_t)id, 2, 0, 0);

-

- // Config for EM410x (RF/64, Manchester, Maxblock=2)

- if (card) {

- // Clock rate is stored in bits 8-15 of the card value

- clock = (card & 0xFF00) >> 8;

- Dbprintf("Clock rate: %d", clock);

- switch (clock)

- {

- case 32:

- clock = T55x7_BITRATE_RF_32;

- break;

- case 16:

- clock = T55x7_BITRATE_RF_16;

- break;

- case 0:

- // A value of 0 is assumed to be 64 for backwards-compatibility

- // Fall through...

- case 64:

- clock = T55x7_BITRATE_RF_64;

- break;

- default:

+ uint32_t data[] = {0, (uint32_t)(id>>32), (uint32_t)(id & 0xFFFFFFFF)};

+

+ clock = (card & 0xFF00) >> 8;

+ clock = (clock == 0) ? 64 : clock;

+ Dbprintf("Clock rate: %d", clock);

+ if (card & 0xFF) { //t55x7

+ clock = GetT55xxClockBit(clock);

+ if (clock == 0) {

Dbprintf("Invalid clock rate: %d", clock);

return;

}

Dbprintf("Invalid clock rate: %d", clock);

return;

}

-

- // Writing configuration for T55x7 tag

- T55xxWriteBlock(clock |

- T55x7_MODULATION_MANCHESTER |

- 2 << T55x7_MAXBLOCK_SHIFT,

- 0, 0, 0);

+ data[0] = clock | T55x7_MODULATION_MANCHESTER | (2 << T55x7_MAXBLOCK_SHIFT);

+ } else { //t5555 (Q5)

+ clock = (clock-2)>>1; //n = (RF-2)/2

+ data[0] = (clock << T5555_BITRATE_SHIFT) | T5555_MODULATION_MANCHESTER | (2 << T5555_MAXBLOCK_SHIFT);

}

- else

- // Writing configuration for T5555(Q5) tag

- T55xxWriteBlock(0x1F << T5555_BITRATE_SHIFT |

- T5555_MODULATION_MANCHESTER |

- 2 << T5555_MAXBLOCK_SHIFT,

- 0, 0, 0);

+

+ WriteT55xx(data, 0, 3);

LED_D_OFF();

Dbprintf("Tag %s written with 0x%08x%08x\n", card ? "T55x7":"T5555",

(uint32_t)(id >> 32), (uint32_t)id);

}

LED_D_OFF();

Dbprintf("Tag %s written with 0x%08x%08x\n", card ? "T55x7":"T5555",

(uint32_t)(id >> 32), (uint32_t)id);

}

-// Clone Indala 64-bit tag by UID to T55x7

-void CopyIndala64toT55x7(int hi, int lo)

-{

-

- //Program the 2 data blocks for supplied 64bit UID

- // and the block 0 for Indala64 format

- T55xxWriteBlock(hi,1,0,0);

- T55xxWriteBlock(lo,2,0,0);

- //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=2)

- T55xxWriteBlock(T55x7_BITRATE_RF_32 |

- T55x7_MODULATION_PSK1 |

- 2 << T55x7_MAXBLOCK_SHIFT,

- 0, 0, 0);

- //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)

- // T5567WriteBlock(0x603E1042,0);

-

- DbpString("DONE!");

-

-}

-

-void CopyIndala224toT55x7(int uid1, int uid2, int uid3, int uid4, int uid5, int uid6, int uid7)

-{

-

- //Program the 7 data blocks for supplied 224bit UID

- // and the block 0 for Indala224 format

- T55xxWriteBlock(uid1,1,0,0);

- T55xxWriteBlock(uid2,2,0,0);

- T55xxWriteBlock(uid3,3,0,0);

- T55xxWriteBlock(uid4,4,0,0);

- T55xxWriteBlock(uid5,5,0,0);

- T55xxWriteBlock(uid6,6,0,0);

- T55xxWriteBlock(uid7,7,0,0);

- //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7)

- T55xxWriteBlock(T55x7_BITRATE_RF_32 |

- T55x7_MODULATION_PSK1 |

- 7 << T55x7_MAXBLOCK_SHIFT,

- 0,0,0);

- //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)

- // T5567WriteBlock(0x603E10E2,0);

-

- DbpString("DONE!");

-

-}

-

//-----------------------------------

// EM4469 / EM4305 routines

//-----------------------------------

// EM4469 / EM4305 routines

//-----------------------------------

#define FWD_CMD_READ 0x9

#define FWD_CMD_DISABLE 0x5

#define FWD_CMD_READ 0x9

#define FWD_CMD_DISABLE 0x5

-

uint8_t forwardLink_data[64]; //array of forwarded bits

uint8_t * forward_ptr; //ptr for forward message preparation

uint8_t fwd_bit_sz; //forwardlink bit counter

uint8_t forwardLink_data[64]; //array of forwarded bits

uint8_t * forward_ptr; //ptr for forward message preparation

uint8_t fwd_bit_sz; //forwardlink bit counter

// see EM4469 spec

//====================================================================

//--------------------------------------------------------------------

// see EM4469 spec

//====================================================================

//--------------------------------------------------------------------

+// VALUES TAKEN FROM EM4x function: SendForward

+// START_GAP = 440; (55*8) cycles at 125Khz (8us = 1cycle)

+// WRITE_GAP = 128; (16*8)

+// WRITE_1 = 256 32*8; (32*8)

+

+// These timings work for 4469/4269/4305 (with the 55*8 above)

+// WRITE_0 = 23*8 , 9*8 SpinDelayUs(23*8);

+

uint8_t Prepare_Cmd( uint8_t cmd ) {

- //--------------------------------------------------------------------

*forward_ptr++ = 0; //start bit

*forward_ptr++ = 0; //second pause for 4050 code

*forward_ptr++ = 0; //start bit

*forward_ptr++ = 0; //second pause for 4050 code

// prepares address bits

// see EM4469 spec

//====================================================================

// prepares address bits

// see EM4469 spec

//====================================================================

-

-//--------------------------------------------------------------------

uint8_t Prepare_Addr( uint8_t addr ) {

- //--------------------------------------------------------------------

register uint8_t line_parity;

// prepares data bits intreleaved with parity bits

// see EM4469 spec

//====================================================================

// prepares data bits intreleaved with parity bits

// see EM4469 spec

//====================================================================

-

-//--------------------------------------------------------------------

uint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) {

- //--------------------------------------------------------------------

register uint8_t line_parity;

register uint8_t column_parity;

register uint8_t line_parity;

register uint8_t column_parity;

fwd_write_ptr = forwardLink_data;

fwd_bit_sz = fwd_bit_count;

fwd_write_ptr = forwardLink_data;

fwd_bit_sz = fwd_bit_count;

- LED_D_ON();

-

- //Field on

- FpgaDownloadAndGo(FPGA_BITSTREAM_LF);

- FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz

- FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);

-

- // Give it a bit of time for the resonant antenna to settle.

- // And for the tag to fully power up

- SpinDelay(150);

+ // Set up FPGA, 125kHz or 95 divisor

+ LFSetupFPGAForADC(95, true);

// force 1st mod pulse (start gap must be longer for 4305)

fwd_bit_sz--; //prepare next bit modulation

fwd_write_ptr++;

FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off

// force 1st mod pulse (start gap must be longer for 4305)

fwd_bit_sz--; //prepare next bit modulation

fwd_write_ptr++;

FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off

- SpinDelayUs(55*8); //55 cycles off (8us each)for 4305

- FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz

+ WaitUS(55*8); //55 cycles off (8us each)for 4305 //another reader has 37 here...

FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on

- SpinDelayUs(16*8); //16 cycles on (8us each)

+ WaitUS(18*8); //18 cycles on (8us each)

// now start writting

while(fwd_bit_sz-- > 0) { //prepare next bit modulation

if(((*fwd_write_ptr++) & 1) == 1)

// now start writting

while(fwd_bit_sz-- > 0) { //prepare next bit modulation

if(((*fwd_write_ptr++) & 1) == 1)

- SpinDelayUs(32*8); //32 cycles at 125Khz (8us each)

+ WaitUS(32*8); //32 cycles at 125Khz (8us each)

else {

//These timings work for 4469/4269/4305 (with the 55*8 above)

FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off

else {

//These timings work for 4469/4269/4305 (with the 55*8 above)

FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off

- SpinDelayUs(23*8); //16-4 cycles off (8us each)

- FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz

+ WaitUS(23*8); //23 cycles off (8us each)

FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on

- SpinDelayUs(9*8); //16 cycles on (8us each)

+ WaitUS(18*8); //18 cycles on (8us each)

}

//Wait for command to complete

SpinDelay(20);

//Wait for command to complete

SpinDelay(20);

-

}

void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {

uint8_t fwd_bit_count;

}

void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {

uint8_t fwd_bit_count;

- uint8_t *dest = BigBuf_get_addr();

- int m=0, i=0;

+ // Clear destination buffer before sending the command

+ BigBuf_Clear_ext(false);

+

+ LED_A_ON();

+ StartTicks();

//If password mode do login

if (PwdMode == 1) EM4xLogin(Pwd);

//If password mode do login

if (PwdMode == 1) EM4xLogin(Pwd);

fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );

fwd_bit_count += Prepare_Addr( Address );

fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );

fwd_bit_count += Prepare_Addr( Address );

- m = BigBuf_max_traceLen();

- // Clear destination buffer before sending the command

- memset(dest, 128, m);

- // Connect the A/D to the peak-detected low-frequency path.

- SetAdcMuxFor(GPIO_MUXSEL_LOPKD);

- // Now set up the SSC to get the ADC samples that are now streaming at us.

- FpgaSetupSsc();

-

SendForward(fwd_bit_count);

-

+ WaitUS(400);

// Now do the acquisition

- i = 0;

- for(;;) {

- if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {

- AT91C_BASE_SSC->SSC_THR = 0x43;

- }

- if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {

- dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;

- i++;

- if (i >= m) break;

- }

+ DoPartialAcquisition(20, true, 6000);

+

FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off

- LED_D_OFF();

+ LED_A_OFF();

+ cmd_send(CMD_ACK,0,0,0,0,0);

}

-void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {

-

+void EM4xWriteWord(uint32_t flag, uint32_t Data, uint32_t Pwd) {

+

+ bool PwdMode = (flag & 0xF);

+ uint8_t Address = (flag >> 8) & 0xFF;

uint8_t fwd_bit_count;

+ //clear buffer now so it does not interfere with timing later

+ BigBuf_Clear_ext(false);

+

+ LED_A_ON();

+ StartTicks();

//If password mode do login

- if (PwdMode == 1) EM4xLogin(Pwd);

+ if (PwdMode) EM4xLogin(Pwd);

forward_ptr = forwardLink_data;

fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE );

forward_ptr = forwardLink_data;

fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE );

SendForward(fwd_bit_count);

//Wait for write to complete

SendForward(fwd_bit_count);

//Wait for write to complete

- SpinDelay(20);

+ //SpinDelay(10);

+

+ WaitUS(6500);

+ //Capture response if one exists

+ DoPartialAcquisition(20, true, 6000);

+

FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off

- LED_D_OFF();

+ LED_A_OFF();

+ cmd_send(CMD_ACK,0,0,0,0,0);

+}

+/*

+Reading a COTAG.

+

+COTAG needs the reader to send a startsequence and the card has an extreme slow datarate.

+because of this, we can "sample" the data signal but we interpreate it to Manchester direct.

+

+READER START SEQUENCE:

+burst 800 us, gap 2.2 msecs

+burst 3.6 msecs gap 2.2 msecs

+burst 800 us gap 2.2 msecs

+pulse 3.6 msecs

+

+This triggers a COTAG tag to response

+*/

+void Cotag(uint32_t arg0) {

+

+#define OFF { FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); WaitUS(2035); }

+#define ON(x) { FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD); WaitUS((x)); }

+

+ uint8_t rawsignal = arg0 & 0xF;

+

+ LED_A_ON();

+

+ // Switching to LF image on FPGA. This might empty BigBuff

+ FpgaDownloadAndGo(FPGA_BITSTREAM_LF);

+

+ //clear buffer now so it does not interfere with timing later

+ BigBuf_Clear_ext(false);

+

+ // Set up FPGA, 132kHz to power up the tag

+ FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 89);

+ FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);

+

+ // Connect the A/D to the peak-detected low-frequency path.

+ SetAdcMuxFor(GPIO_MUXSEL_LOPKD);

+

+ // Now set up the SSC to get the ADC samples that are now streaming at us.

+ FpgaSetupSsc();

+

+ // start clock - 1.5ticks is 1us

+ StartTicks();

+

+ //send COTAG start pulse

+ ON(740) OFF

+ ON(3330) OFF

+ ON(740) OFF

+ ON(1000)

+

+ switch(rawsignal) {

+ case 0: doCotagAcquisition(50000); break;

+ case 1: doCotagAcquisitionManchester(); break;

+ case 2: DoAcquisition_config(TRUE); break;

+ }

+

+ // Turn the field off

+ FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off

+ cmd_send(CMD_ACK,0,0,0,0,0);

+ LED_A_OFF();

}