+ hi = lo = size = idx = 0;
+ clk = invert = errCnt = 0;
+ }
+ FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
+ DbpString("Stopped");
+ if (ledcontrol) LED_A_OFF();
+}
+
+void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
+{
+ uint8_t *dest = BigBuf_get_addr();
+ int idx=0;
+ uint32_t code=0, code2=0;
+ uint8_t version=0;
+ uint8_t facilitycode=0;
+ uint16_t number=0;
+ int dummyIdx=0;
+ //clear read buffer
+ BigBuf_Clear_keep_EM();
+ // Configure to go in 125Khz listen mode
+ LFSetupFPGAForADC(95, true);
+
+ while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
+ WDT_HIT();
+ if (ledcontrol) LED_A_ON();
+ DoAcquisition_default(-1,true);
+ //fskdemod and get start index
+ WDT_HIT();
+ idx = IOdemodFSK(dest, BigBuf_max_traceLen(), &dummyIdx);
+ if (idx<0) continue;
+ //valid tag found
+
+ //Index map
+ //0 10 20 30 40 50 60
+ //| | | | | | |
+ //01234567 8 90123456 7 89012345 6 78901234 5 67890123 4 56789012 3 45678901 23
+ //-----------------------------------------------------------------------------
+ //00000000 0 11110000 1 facility 1 version* 1 code*one 1 code*two 1 ???????? 11
+ //
+ //XSF(version)facility:codeone+codetwo
+ //Handle the data
+ if(findone){ //only print binary if we are doing one
+ Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx], dest[idx+1], dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7],dest[idx+8]);
+ Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15],dest[idx+16],dest[idx+17]);
+ Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23],dest[idx+24],dest[idx+25],dest[idx+26]);
+ Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+27],dest[idx+28],dest[idx+29],dest[idx+30],dest[idx+31],dest[idx+32],dest[idx+33],dest[idx+34],dest[idx+35]);
+ Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+36],dest[idx+37],dest[idx+38],dest[idx+39],dest[idx+40],dest[idx+41],dest[idx+42],dest[idx+43],dest[idx+44]);
+ Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+45],dest[idx+46],dest[idx+47],dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53]);
+ Dbprintf("%d%d%d%d%d%d%d%d %d%d",dest[idx+54],dest[idx+55],dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]);
+ }
+ code = bytebits_to_byte(dest+idx,32);
+ code2 = bytebits_to_byte(dest+idx+32,32);
+ version = bytebits_to_byte(dest+idx+27,8); //14,4
+ facilitycode = bytebits_to_byte(dest+idx+18,8);
+ number = (bytebits_to_byte(dest+idx+36,8)<<8)|(bytebits_to_byte(dest+idx+45,8)); //36,9
+
+ Dbprintf("XSF(%02d)%02x:%05d (%08x%08x)",version,facilitycode,number,code,code2);
+ // if we're only looking for one tag
+ if (findone){
+ if (ledcontrol) LED_A_OFF();
+ //LED_A_OFF();
+ *high=code;
+ *low=code2;
+ break;
+ }
+ code=code2=0;
+ version=facilitycode=0;
+ number=0;
+ idx=0;
+
+ WDT_HIT();
+ }
+ FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
+ DbpString("Stopped");
+ if (ledcontrol) LED_A_OFF();
+}
+
+/*------------------------------
+ * T5555/T5557/T5567/T5577 routines
+ *------------------------------
+ * NOTE: T55x7/T5555 configuration register definitions moved to protocols.h
+ *
+ * Relevant communication times in microsecond
+ * To compensate antenna falling times shorten the write times
+ * and enlarge the gap ones.
+ * Q5 tags seems to have issues when these values changes.
+ */
+ /*
+ // Original Timings for reference
+
+#define START_GAP 31*8 // was 250 // SPEC: 1*8 to 50*8 - typ 15*8 (or 15fc)
+#define WRITE_GAP 20*8 // was 160 // SPEC: 1*8 to 20*8 - typ 10*8 (or 10fc)
+#define WRITE_0 18*8 // was 144 // SPEC: 16*8 to 32*8 - typ 24*8 (or 24fc)
+#define WRITE_1 50*8 // was 400 // SPEC: 48*8 to 64*8 - typ 56*8 (or 56fc) 432 for T55x7; 448 for E5550
+#define READ_GAP 15*8
+*/
+
+// Structure to hold Timing values. In future will be simplier to add user changable timings.
+typedef struct {
+ uint16_t START_GAP;
+ uint16_t WRITE_GAP;
+ uint16_t WRITE_0;
+ uint16_t WRITE_1;
+ uint16_t WRITE_2;
+ uint16_t WRITE_3;
+ uint16_t READ_GAP;
+} T55xx_Timing;
+
+/*
+ T5577 Timeing from datasheet for reference
+
+ Fixed bit length
+ ----------------
+ Normal Down Link Fast Downlink
+ Min Typ Max Min Typ Max
+ Start gap 8 15 50 8 15 50
+ Write gap 8 10 20 8 10 20
+ 0 data 16 24 32 8 12 16
+ 1 data 48 56 64 24 28 32
+
+
+ Long Leading Reference
+ ----------------------
+ Normal Down Link Fast Downlink
+ Min Typ Max Min Typ Max
+ Start gap 8 10 50 8 10 50
+ Write gap 8 10 20 8 10 20
+ Reference(r) 152 160 168 140 144 148
+ 136 + 0 data 132 + 0 data
+ 0 data r - 143 r - 136 r - 128 r - 135 r - 132 r - 124
+ 1 data r - 111 r - 104 r - 96 r - 119 r - 116 r - 112
+
+
+ Leading Zero Reference
+ ----------------------
+ Normal Down Link Fast Downlink
+ Min Typ Max Min Typ Max
+ Start gap 8 10 50 8 10 50
+ Write gap 8 10 20 8 10 20
+ Reference(r) 12 - 72 8 - 68
+ 0 data r - 7 r r + 8 r - 3 r r + 4
+ 1 data r + 9 r + 16 r + 24 r + 5 r + 8 r + 12
+
+
+ 1 of 4 Coding
+ -------------
+ Normal Down Link Fast Downlink
+ Min Typ Max Min Typ Max
+ Start gap 8 10 50 8 10 50
+ Write gap 8 10 20 8 10 20
+ Reference(r) 8 - 68 12 - 72
+ 00 data r - 7 r r + 8 r - 3 r r + 4
+ 01 data r + 9 r + 16 r + 24 r + 5 r + 8 r + 12
+ 10 data r + 25 r + 32 r + 40 r + 13 r + 16 r + 20
+ 11 data r + 41 r + 48 r + 56 r + 21 r + 24 r + 28
+
+*/
+
+// Set Initial/Default Values. Note: *8 can occure when used. This should keep things simplier here.
+T55xx_Timing T55xx_Timing_FixedBit = { 31 * 8 , 20 * 8 , 18 * 8 , 50 * 8 , 0 , 0 , 15 * 8 };
+T55xx_Timing T55xx_Timing_LLR = { 31 * 8 , 20 * 8 , 18 * 8 , 50 * 8 , 0 , 0 , 15 * 8 };
+T55xx_Timing T55xx_Timing_Leading0 = { 31 * 8 , 20 * 8 , 18 * 8 , 40 * 8 , 0 , 0 , 15 * 8 };
+T55xx_Timing T55xx_Timing_1of4 = { 31 * 8 , 20 * 8 , 18 * 8 , 34 * 8 , 50 * 8 , 66 * 8 , 15 * 8 };
+
+
+// Some defines for readability
+#define T55xx_LongLeadingReference 4 // Value to tell Write Bit to send long reference
+#define T55xx_DLMode_Fixed 0 // Default Mode
+#define T55xx_DLMode_LLR 1 // Long Leading Reference
+#define T55xx_DLMode_Leading0 2 // Leading Zero
+#define T55xx_DLMode_1of4 3 // 1 of 4
+
+void TurnReadLFOn(int delay) {
+ FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
+ // Give it a bit of time for the resonant antenna to settle.
+ WaitUS(delay); //155*8 //50*8
+}
+
+// Write one bit to card
+void T55xxWriteBit(int bit, T55xx_Timing *Timings) {
+
+ // If bit = 4 Send Long Leading Reference which is 138 + WRITE_0
+
+ switch (bit){
+ case 0 : TurnReadLFOn(Timings->WRITE_0); break; // Send bit 0/00
+ case 1 : TurnReadLFOn(Timings->WRITE_1); break; // Send bit 1/01
+ case 2 : TurnReadLFOn(Timings->WRITE_2); break; // Send bits 10
+ case 3 : TurnReadLFOn(Timings->WRITE_3); break; // Send bits 11
+ case 4 : TurnReadLFOn(Timings->WRITE_0 + (136 * 8)); break; // Send Long Leading Reference
+ }
+ FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
+ WaitUS(Timings->WRITE_GAP);
+}
+
+
+// Function to abstract an Arbitrary length byte array to store bit pattern.
+// bit_array - Array to hold data/bit pattern
+// start_offset - bit location to start storing new bits.
+// data - upto 32 bits of data to store
+// num_bits - how many bits (low x bits of data) Max 32 bits at a time
+// max_len - how many bytes can the bit_array hold (ensure no buffer overflow)
+// returns "Next" bit offset / bits stored (for next store)
+int T55xx_SetBits (uint8_t *bit_array, int start_offset, uint32_t data , int num_bits, int max_len)
+{
+ int bit,byte_idx, bit_idx;
+ int offset;
+ int NextOffset = start_offset;
+
+ // Check if data will fit.
+ if ((start_offset + num_bits) <= (max_len*8)) {
+
+ // Loop through the data and store
+ for (offset = (num_bits-1); offset >= 0; offset--) {
+
+ bit = (data >> offset) & 1; // Get data bit value (0/1)
+ byte_idx = (NextOffset / 8); // Get Array Byte Index to Store
+ bit_idx = NextOffset - (byte_idx * 8); // Get Bit Index to set/clr
+
+ // If set (1) we OR, if clear (0) we AND with inverse
+ // Dbprintf ("Add Bit : %d at byte %d bit %d",bit,byte_idx,bit_idx);
+ if (bit == 1)
+ bit_array[byte_idx] |= (1 << bit_idx); // Set the bit to 1
+
+ else
+ bit_array[byte_idx] &= (0xff ^ (1 << bit_idx)); // Set the bit to 0 (clr)
+
+ NextOffset++;
+ }
+ }
+ else
+ Dbprintf ("Too Many Bits to fit into bit buffer");
+ return NextOffset;
+}
+
+// Send T5577 reset command then read stream (see if we can identify the start of the stream)
+void T55xxResetRead(void) {
+ LED_A_ON();
+ //clear buffer now so it does not interfere with timing later
+ BigBuf_Clear_keep_EM();
+
+ // Set up FPGA, 125kHz
+ LFSetupFPGAForADC(95, true);
+ StartTicks();
+ // make sure tag is fully powered up...
+ WaitMS(5);
+
+ // Trigger T55x7 in mode.
+ FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
+ WaitUS(T55xx_Timing_FixedBit.START_GAP);
+
+ // reset tag - op code 00
+ T55xxWriteBit(0,&T55xx_Timing_FixedBit);
+ T55xxWriteBit(0,&T55xx_Timing_FixedBit);
+
+ TurnReadLFOn(T55xx_Timing_FixedBit.READ_GAP);
+
+ // Acquisition
+ DoPartialAcquisition(0, true, BigBuf_max_traceLen(), 0);
+
+ // Turn the field off
+ FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
+ cmd_send(CMD_ACK,0,0,0,0,0);
+ LED_A_OFF();
+}
+
+// Send one downlink command to the card
+void T55xx_SendCMD (uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t arg) { //, bool read_cmd) {//, struct T55xx_Timing *Timing) {
+
+ /*
+ arg bits
+ xxxxxxx1 0x01 PwdMode
+ xxxxxx1x 0x02 Page
+ xxxxx1xx 0x04 testMode
+ xxx11xxx 0x18 downlink mode
+ xx1xxxxx 0x20 reg_readmode
+ x1xxxxxx 0x40 called for a read, so no data packet
+
+ */
+ bool PwdMode = ((arg & 0x01) == 0x01);
+ uint8_t Page = (arg & 0x02) >> 1;
+ bool testMode = ((arg & 0x04) == 0x04);
+ uint8_t downlink_mode = (arg >> 3) & 0x03;;
+ bool reg_readmode = ((arg & 0x20) == 0x20);
+ bool read_cmd = ((arg & 0x40) == 0x40);
+
+ int i = 0;
+ uint8_t BitStream[10]; // Max Downlink Command size ~75 bits, so 10 bytes (80 bits)
+ uint8_t BitStreamLen;
+ int byte_idx, bit_idx;
+ T55xx_Timing *Timing;
+
+
+ // Assigning Downlink Timeing for write
+ switch (downlink_mode)
+ {
+ case T55xx_DLMode_Fixed : Timing = &T55xx_Timing_FixedBit; break;
+ case T55xx_DLMode_LLR : Timing = &T55xx_Timing_LLR; break;
+ case T55xx_DLMode_Leading0 : Timing = &T55xx_Timing_Leading0; break;
+ case T55xx_DLMode_1of4 : Timing = &T55xx_Timing_1of4; break;
+ default:
+ Timing = &T55xx_Timing_FixedBit;
+ }
+
+ // Build Bit Stream to send.
+ memset (BitStream,0x00,sizeof(BitStream));
+
+ BitStreamLen = 0;
+
+ // Add Leading 0 and 1 of 4 reference bit
+ if ((downlink_mode == T55xx_DLMode_Leading0) || (downlink_mode == T55xx_DLMode_1of4))
+ BitStreamLen = T55xx_SetBits (BitStream, BitStreamLen, 0, 1,sizeof(BitStream));
+
+ // Add extra reference 0 for 1 of 4
+ if (downlink_mode == T55xx_DLMode_1of4)
+ BitStreamLen = T55xx_SetBits (BitStream, BitStreamLen, 0, 1,sizeof(BitStream));
+
+ // Add Opcode
+ if (testMode) Dbprintf("TestMODE");
+ BitStreamLen = T55xx_SetBits (BitStream, BitStreamLen,testMode ? 0 : 1 , 1,sizeof(BitStream));
+ BitStreamLen = T55xx_SetBits (BitStream, BitStreamLen,testMode ? 1 : Page , 1,sizeof(BitStream));
+
+ if (PwdMode) {
+
+ // Leading 0 and 1 of 4 00 fixed bits if passsword used
+ if ((downlink_mode == T55xx_DLMode_Leading0) || (downlink_mode == T55xx_DLMode_1of4)) {
+ BitStreamLen = T55xx_SetBits (BitStream, BitStreamLen, 0, 1,sizeof(BitStream));
+ BitStreamLen = T55xx_SetBits (BitStream, BitStreamLen, 0, 1,sizeof(BitStream));
+ }
+ BitStreamLen = T55xx_SetBits (BitStream, BitStreamLen, Pwd, 32,sizeof(BitStream));
+
+ }
+ // Add Lock bit
+ BitStreamLen = T55xx_SetBits (BitStream, BitStreamLen, 0, 1,sizeof(BitStream));
+
+ // Add Data if a write command
+ if (!read_cmd) BitStreamLen = T55xx_SetBits (BitStream, BitStreamLen, Data, 32,sizeof(BitStream));
+
+ // Add Address
+ if (!reg_readmode) BitStreamLen = T55xx_SetBits (BitStream, BitStreamLen, Block, 3,sizeof(BitStream));
+
+
+
+ // Send Bits to T55xx
+
+ // Set up FPGA, 125kHz
+ LFSetupFPGAForADC(95, true);
+ StartTicks();
+ // make sure tag is fully powered up...
+ WaitMS(5);
+ // Trigger T55x7 in mode.
+ FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
+ WaitUS(Timing->START_GAP);
+
+
+ // If long leading 0 send long reference pulse
+ if (downlink_mode == T55xx_DLMode_LLR)
+ T55xxWriteBit (T55xx_LongLeadingReference,Timing); // Send Long Leading Start Reference
+
+ uint8_t SendBits;
+
+ if (downlink_mode == T55xx_DLMode_1of4) { // 1 of 4 need to send 2 bits at a time
+ for (i = 0; i < BitStreamLen; i+=2) {
+ byte_idx = i / 8;
+ bit_idx = i - (byte_idx * 8);
+ SendBits = ((BitStream[byte_idx] >> bit_idx) & 1) << 1;
+
+ byte_idx = (i+1) / 8;
+ bit_idx = (i+1) - (byte_idx * 8);
+ SendBits += (BitStream[byte_idx] >> bit_idx) & 1;
+
+ T55xxWriteBit (SendBits,Timing);
+ }
+ }
+ else {
+ for (i = 0; i < BitStreamLen; i++) {
+ byte_idx = i / 8;
+ bit_idx = i - (byte_idx * 8);
+ SendBits = (BitStream[byte_idx] >> bit_idx) & 1;
+ T55xxWriteBit (SendBits,Timing);
+ }
+ }
+
+}
+
+// Write one card block in page 0, no lock
+void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t arg) {
+ /*
+ arg bits
+ xxxxxxx1 0x01 PwdMode
+ xxxxxx1x 0x02 Page
+ xxxxx1xx 0x04 testMode
+ xxx11xxx 0x18 downlink mode
+ xx1xxxxx 0x20 reg_readmode
+ x1xxxxxx 0x40 called for a read, so no data packet
+ */
+
+ bool testMode = ((arg & 0x04) == 0x04);
+ arg &= (0xff ^ 0x40); // Called for a write, so ensure it is clear/0
+
+ LED_A_ON ();
+ T55xx_SendCMD (Data, Block, Pwd, arg) ;//, false);
+
+ // Perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
+ // so wait a little more)
+
+ // "there is a clock delay before programming"
+ // - programming takes ~5.6ms for t5577 ~18ms for E5550 or t5567
+ // so we should wait 1 clock + 5.6ms then read response?
+ // but we need to know we are dealing with t5577 vs t5567 vs e5550 (or q5) marshmellow...
+ if (testMode) {
+ //TESTMODE TIMING TESTS:
+ // <566us does nothing
+ // 566-568 switches between wiping to 0s and doing nothing
+ // 5184 wipes and allows 1 block to be programmed.
+ // indefinite power on wipes and then programs all blocks with bitshifted data sent.
+ TurnReadLFOn(5184);
+
+ } else {
+ TurnReadLFOn(20 * 1000);
+ //could attempt to do a read to confirm write took
+ // as the tag should repeat back the new block
+ // until it is reset, but to confirm it we would
+ // need to know the current block 0 config mode for
+ // modulation clock an other details to demod the response...
+ // response should be (for t55x7) a 0 bit then (ST if on)
+ // block data written in on repeat until reset.
+
+ //DoPartialAcquisition(20, true, 12000);
+ }
+ // turn field off
+ FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
+
+ cmd_send(CMD_ACK,0,0,0,0,0);
+
+ LED_A_OFF ();
+}
+
+// Read one card block in page [page]
+void T55xxReadBlock (uint16_t arg0, uint8_t Block, uint32_t Pwd) {//, struct T55xx_Timing *Timing) {
+
+ LED_A_ON();
+
+ /*
+ arg bits
+ xxxxxxx1 0x01 PwdMode
+ xxxxxx1x 0x02 Page
+ xxxxx1xx 0x04 testMode
+ xxx11xxx 0x18 downlink mode
+ xx1xxxxx 0x20 reg_readmode
+ x1xxxxxx 0x40 called for a read, so no data packet
+ */
+
+ // Set Read Flag to ensure SendCMD does not add "data" to the packet
+ arg0 |= 0x40;
+
+
+ if (Block == 0xff) arg0 |= 0x20;
+
+ //make sure block is at max 7
+ Block &= 0x7;
+ //clear buffer now so it does not interfere with timing later
+ BigBuf_Clear_ext(false);
+
+ T55xx_SendCMD (0, Block, Pwd, arg0); //, true);
+
+
+ // Turn field on to read the response
+ // 137*8 seems to get to the start of data pretty well...
+ // but we want to go past the start and let the repeating data settle in...
+ TurnReadLFOn(210*8);
+
+ // Acquisition
+ // Now do the acquisition
+ DoPartialAcquisition(0, true, 12000, 0);
+
+ // Turn the field off
+ FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
+ cmd_send(CMD_ACK,0,0,0,0,0);
+
+ LED_A_OFF();
+}
+
+void T55xxWakeUp(uint32_t Pwd){
+ LED_B_ON();
+ uint32_t i = 0;
+
+ // Set up FPGA, 125kHz
+ LFSetupFPGAForADC(95, true);
+ StartTicks();
+ // make sure tag is fully powered up...
+ WaitMS(5);
+
+ // Trigger T55x7 Direct Access Mode
+ FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
+ WaitUS(T55xx_Timing_FixedBit.START_GAP);
+
+ // Opcode 10
+ T55xxWriteBit(1,&T55xx_Timing_FixedBit);
+ T55xxWriteBit(0,&T55xx_Timing_FixedBit); //Page 0
+
+ // Send Pwd
+
+ for (i = 0x80000000; i != 0; i >>= 1)
+ T55xxWriteBit(Pwd & i,&T55xx_Timing_FixedBit);
+
+ // Turn and leave field on to let the begin repeating transmission
+ TurnReadLFOn(20*1000);
+}
+
+/*-------------- Cloning routines -----------*/
+
+void WriteT55xx(uint32_t *blockdata, uint8_t startblock, uint8_t numblocks) {
+ // write last block first and config block last (if included)
+ for (uint8_t i = numblocks+startblock; i > startblock; i--) {
+ T55xxWriteBlock(blockdata[i-1],i-1,0,0);//,false); //,&T55xx_Timing_FixedBit);
+ // T55xx_SendCMD (blockdata[i-1],i-1,0,0);//,false); //,&T55xx_Timing_FixedBit);
+ }
+}
+
+// Copy a HID-like card (e.g. HID Proximity, Paradox) to a T55x7 compatible card
+void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT, uint8_t preamble) {
+ uint32_t data[] = {0,0,0,0,0,0,0};
+ uint8_t last_block = 0;
+
+ if (longFMT) {
+ // Ensure no more than 84 bits supplied
+ if (hi2>0xFFFFF) {
+ DbpString("Tags can only have 84 bits.");
+ return;
+ }
+ // Build the 6 data blocks for supplied 84bit ID
+ last_block = 6;
+ // load preamble & long format identifier (9E manchester encoded)
+ data[1] = (preamble << 24) | 0x96A900 | (manchesterEncode2Bytes((hi2 >> 16) & 0xF) & 0xFF);
+ // load raw id from hi2, hi, lo to data blocks (manchester encoded)
+ data[2] = manchesterEncode2Bytes(hi2 & 0xFFFF);
+ data[3] = manchesterEncode2Bytes(hi >> 16);
+ data[4] = manchesterEncode2Bytes(hi & 0xFFFF);
+ data[5] = manchesterEncode2Bytes(lo >> 16);
+ data[6] = manchesterEncode2Bytes(lo & 0xFFFF);
+ } else {
+ // Ensure no more than 44 bits supplied
+ if (hi>0xFFF) {
+ DbpString("Tags can only have 44 bits.");
+ return;
+ }
+ // Build the 3 data blocks for supplied 44bit ID
+ last_block = 3;
+ // load preamble
+ data[1] = (preamble << 24) | (manchesterEncode2Bytes(hi) & 0xFFFFFF);
+ data[2] = manchesterEncode2Bytes(lo >> 16);
+ data[3] = manchesterEncode2Bytes(lo & 0xFFFF);