Fixed several issues found using a coverity-scan

[proxmark3-svn] / armsrc / lfops.c

diff --git a/armsrc/lfops.c b/armsrc/lfops.c
index d29ec37551658effd1ee580d36f1e4932df95f49..74f04913e6e66760e5a617860110e412dd900192 100644 (file)
--- a/armsrc/lfops.c
+++ b/armsrc/lfops.c
@@ -15,7 +15,13 @@
 #include "crc16.h"
 #include "string.h"
 
 #include "crc16.h"
 #include "string.h"
 

-// split into two routines so we can avoid timing issues after sending commands //
+
+/**
+* Does the sample acquisition. If threshold is specified, the actual sampling 
+* is not commenced until the threshold has been reached. 
+* @param trigger_threshold - the threshold
+* @param silent - is true, now outputs are made. If false, dbprints the status
+*/

 void DoAcquisition125k_internal(int trigger_threshold,bool silent)
 {
        uint8_t *dest = (uint8_t *)BigBuf;
 void DoAcquisition125k_internal(int trigger_threshold,bool silent)
 {
        uint8_t *dest = (uint8_t *)BigBuf;


@@ -46,12 +52,21 @@ void DoAcquisition125k_internal(int trigger_threshold,bool silent)
                
        }
 }
                
        }
 }

+/**
+* Perform sample aquisition. 
+*/

 void DoAcquisition125k(int trigger_threshold)
 {
        DoAcquisition125k_internal(trigger_threshold, false);
 }
 
 void DoAcquisition125k(int trigger_threshold)
 {
        DoAcquisition125k_internal(trigger_threshold, false);
 }
 

-//void SetupToAcquireRawAdcSamples(int divisor)
+/**
+* Setup the FPGA to listen for samples. This method downloads the FPGA bitstream 
+* if not already loaded, sets divisor and starts up the antenna. 
+* @param divisor : 1, 88> 255 or negative ==> 134.8 KHz
+*                                 0 or 95 ==> 125 KHz
+*                                 
+**/

 void LFSetupFPGAForADC(int divisor, bool lf_field)
 {
        FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
 void LFSetupFPGAForADC(int divisor, bool lf_field)
 {
        FpgaDownloadAndGo(FPGA_BITSTREAM_LF);


@@ -71,46 +86,46 @@ void LFSetupFPGAForADC(int divisor, bool lf_field)
        // Now set up the SSC to get the ADC samples that are now streaming at us.
        FpgaSetupSsc();
 }
        // Now set up the SSC to get the ADC samples that are now streaming at us.
        FpgaSetupSsc();
 }

-
+/**
+* Initializes the FPGA, and acquires the samples. 
+**/

 void AcquireRawAdcSamples125k(int divisor)
 {
        LFSetupFPGAForADC(divisor, true);
        // Now call the acquisition routine
        DoAcquisition125k_internal(-1,false);
 }
 void AcquireRawAdcSamples125k(int divisor)
 {
        LFSetupFPGAForADC(divisor, true);
        // Now call the acquisition routine
        DoAcquisition125k_internal(-1,false);
 }

+/**
+* Initializes the FPGA for snoop-mode, and acquires the samples. 
+**/
+

 void SnoopLFRawAdcSamples(int divisor, int trigger_threshold)
 {
        LFSetupFPGAForADC(divisor, false);
 void SnoopLFRawAdcSamples(int divisor, int trigger_threshold)
 {
        LFSetupFPGAForADC(divisor, false);

-       DoAcquisition125k(trigger_threshold, false);
-}
-
-
+       DoAcquisition125k(trigger_threshold);

 }
 
 void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1, uint8_t *command)
 {
 }
 
 void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1, uint8_t *command)
 {

-       int at134khz;

 
        /* Make sure the tag is reset */
        FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
        SpinDelay(2500);
 
 
        /* Make sure the tag is reset */
        FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
        SpinDelay(2500);
 

+
+       int divisor_used = 95; // 125 KHz

        // see if 'h' was specified
        // see if 'h' was specified

+

        if (command[strlen((char *) command) - 1] == 'h')
        if (command[strlen((char *) command) - 1] == 'h')

-               at134khz = TRUE;
-       else
-               at134khz = FALSE;
+               divisor_used = 88; // 134.8 KHz

 
 

-       if (at134khz)
-               FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
-       else
-               FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz

 
 

+       FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor_used); 

        FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
        FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);

-

        // Give it a bit of time for the resonant antenna to settle.
        SpinDelay(50);
        // Give it a bit of time for the resonant antenna to settle.
        SpinDelay(50);

+

        // And a little more time for the tag to fully power up
        SpinDelay(2000);
 
        // And a little more time for the tag to fully power up
        SpinDelay(2000);
 


@@ -122,10 +137,7 @@ void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1,
                FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
                LED_D_OFF();
                SpinDelayUs(delay_off);
                FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
                LED_D_OFF();
                SpinDelayUs(delay_off);

-               if (at134khz)
-                       FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
-               else
-                       FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
+               FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor_used); 

 
                FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
                LED_D_ON();
 
                FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
                LED_D_ON();


@@ -137,10 +149,7 @@ void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1,
        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
        LED_D_OFF();
        SpinDelayUs(delay_off);
        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
        LED_D_OFF();
        SpinDelayUs(delay_off);

-       if (at134khz)
-               FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
-       else
-               FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
+       FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor_used); 

 
        FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
 
 
        FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
 


@@ -702,21 +711,19 @@ void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
        size_t size=0,idx=0; //, found=0;
        uint32_t hi2=0, hi=0, lo=0;
 
        size_t size=0,idx=0; //, found=0;
        uint32_t hi2=0, hi=0, lo=0;
 

+       // Configure to go in 125Khz listen mode
+       LFSetupFPGAForADC(95, true);

 
        while(!BUTTON_PRESS()) {
 
 
        while(!BUTTON_PRESS()) {
 

-               // Configure to go in 125Khz listen mode
-               LFSetupFPGAForADC(0, true)
-

                WDT_HIT();
                if (ledcontrol) LED_A_ON();
 
                WDT_HIT();
                if (ledcontrol) LED_A_ON();
 

-               DoAcquisition125k_internal(true);
+               DoAcquisition125k_internal(-1,true);

                size  = sizeof(BigBuf);
 
                // FSK demodulator
                size = fsk_demod(dest, size);
                size  = sizeof(BigBuf);
 
                // FSK demodulator
                size = fsk_demod(dest, size);

-               WDT_HIT();

 
                // we now have a set of cycle counts, loop over previous results and aggregate data into bit patterns
                // 1->0 : fc/8 in sets of 6
 
                // we now have a set of cycle counts, loop over previous results and aggregate data into bit patterns
                // 1->0 : fc/8 in sets of 6


@@ -737,7 +744,8 @@ void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
                                idx+=sizeof(frame_marker_mask);
 
                                while(dest[idx] != dest[idx+1] && idx < size-2)
                                idx+=sizeof(frame_marker_mask);
 
                                while(dest[idx] != dest[idx+1] && idx < size-2)

-                               {       // Keep going until next frame marker (or error)
+                               {       
+                                       // Keep going until next frame marker (or error)

                                        // Shift in a bit. Start by shifting high registers
                                        hi2 = (hi2<<1)|(hi>>31);
                                        hi = (hi<<1)|(lo>>31);
                                        // Shift in a bit. Start by shifting high registers
                                        hi2 = (hi2<<1)|(hi>>31);
                                        hi = (hi<<1)|(lo>>31);


@@ -752,16 +760,20 @@ void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
                                }
                                //Dbprintf("Num shifts: %d ", numshifts);
                                // Hopefully, we read a tag and  hit upon the next frame marker
                                }
                                //Dbprintf("Num shifts: %d ", numshifts);
                                // Hopefully, we read a tag and  hit upon the next frame marker

-                               if ( memcmp(dest+idx, frame_marker_mask, sizeof(frame_marker_mask)) == 0)
+                               if(idx + sizeof(frame_marker_mask) < size)

                                {
                                {

-                                       if (hi2 != 0){
-                                               Dbprintf("TAG ID: %x%08x%08x (%d)",
-                                                        (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
-                                       }
-                                       else {
-                                               Dbprintf("TAG ID: %x%08x (%d)",
-                                                (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
+                                       if ( memcmp(dest+idx, frame_marker_mask, sizeof(frame_marker_mask)) == 0)
+                                       {
+                                               if (hi2 != 0){
+                                                       Dbprintf("TAG ID: %x%08x%08x (%d)",
+                                                                (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
+                                               }
+                                               else {
+                                                       Dbprintf("TAG ID: %x%08x (%d)",
+                                                        (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
+                                               }

                                        }
                                        }

+

                                }
 
                                // reset
                                }
 
                                // reset


@@ -798,21 +810,20 @@ void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
        size_t size=0, idx=0;
        uint32_t code=0, code2=0;
 
        size_t size=0, idx=0;
        uint32_t code=0, code2=0;
 

+       // Configure to go in 125Khz listen mode
+       LFSetupFPGAForADC(95, true);

 
        while(!BUTTON_PRESS()) {
 
 
        while(!BUTTON_PRESS()) {
 

-               // Configure to go in 125Khz listen mode
-               LFSetupFPGAForADC(0, true);

 
                WDT_HIT();
                if (ledcontrol) LED_A_ON();
 
 
                WDT_HIT();
                if (ledcontrol) LED_A_ON();
 

-               DoAcquisition125k_internal(true);
+               DoAcquisition125k_internal(-1,true);

                size  = sizeof(BigBuf);
 
                // FSK demodulator
                size = fsk_demod(dest, size);
                size  = sizeof(BigBuf);
 
                // FSK demodulator
                size = fsk_demod(dest, size);

-               WDT_HIT();

 
                // we now have a set of cycle counts, loop over previous results and aggregate data into bit patterns
                // 1->0 : fc/8 in sets of 7
 
                // we now have a set of cycle counts, loop over previous results and aggregate data into bit patterns
                // 1->0 : fc/8 in sets of 7