X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/proxmark3-svn/blobdiff_plain/15c4dc5ace24e6081d1597b011148f156cdd599e..90e278d3daf11b501043d7ae628a25aeb0227420:/armsrc/fpgaloader.c?ds=inline

diff --git a/armsrc/fpgaloader.c b/armsrc/fpgaloader.c
index 8ce07dd3..077b378a 100644
--- a/armsrc/fpgaloader.c
+++ b/armsrc/fpgaloader.c
@@ -1,11 +1,18 @@
 //-----------------------------------------------------------------------------
+// Jonathan Westhues, April 2006
+// iZsh <izsh at fail0verflow.com>, 2014
+//
+// This code is licensed to you under the terms of the GNU GPL, version 2 or,
+// at your option, any later version. See the LICENSE.txt file for the text of
+// the license.
+//-----------------------------------------------------------------------------
 // Routines to load the FPGA image, and then to configure the FPGA's major
 // mode once it is configured.
-//
-// Jonathan Westhues, April 2006
 //-----------------------------------------------------------------------------
-#include <proxmark3.h>
+#include "proxmark3.h"
 #include "apps.h"
+#include "util.h"
+#include "string.h"
 
 //-----------------------------------------------------------------------------
 // Set up the Serial Peripheral Interface as master
@@ -108,14 +115,12 @@ void FpgaSetupSsc(void)
 	AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(1) | SSC_CLOCK_MODE_START(1);
 
 	// 8 bits per transfer, no loopback, MSB first, 1 transfer per sync
-	// pulse, no output sync, start on positive-going edge of sync
-	AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(8) |
-		AT91C_SSC_MSBF | SSC_FRAME_MODE_WORDS_PER_TRANSFER(0);
+	// pulse, no output sync
+	AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(8) |	AT91C_SSC_MSBF | SSC_FRAME_MODE_WORDS_PER_TRANSFER(0);
 
 	// clock comes from TK pin, no clock output, outputs change on falling
-	// edge of TK, start on rising edge of TF
-	AT91C_BASE_SSC->SSC_TCMR = SSC_CLOCK_MODE_SELECT(2) |
-		SSC_CLOCK_MODE_START(5);
+	// edge of TK, sample on rising edge of TK, start on positive-going edge of sync
+	AT91C_BASE_SSC->SSC_TCMR = SSC_CLOCK_MODE_SELECT(2) |	SSC_CLOCK_MODE_START(5);
 
 	// tx framing is the same as the rx framing
 	AT91C_BASE_SSC->SSC_TFMR = AT91C_BASE_SSC->SSC_RFMR;
@@ -129,13 +134,20 @@ void FpgaSetupSsc(void)
 // ourselves, not to another buffer). The stuff to manipulate those buffers
 // is in apps.h, because it should be inlined, for speed.
 //-----------------------------------------------------------------------------
-void FpgaSetupSscDma(BYTE *buf, int len)
+bool FpgaSetupSscDma(uint8_t *buf, int len)
 {
-	AT91C_BASE_PDC_SSC->PDC_RPR = (DWORD)buf;
-	AT91C_BASE_PDC_SSC->PDC_RCR = len;
-	AT91C_BASE_PDC_SSC->PDC_RNPR = (DWORD)buf;
-	AT91C_BASE_PDC_SSC->PDC_RNCR = len;
-	AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTEN;
+	if (buf == NULL) {
+        return false;
+    }
+
+	AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS;	// Disable DMA Transfer
+	AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) buf;		// transfer to this memory address
+	AT91C_BASE_PDC_SSC->PDC_RCR = len;					// transfer this many bytes
+	AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) buf;		// next transfer to same memory address
+	AT91C_BASE_PDC_SSC->PDC_RNCR = len;					// ... with same number of bytes
+	AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTEN;		// go!
+    
+    return true;
 }
 
 static void DownloadFPGA_byte(unsigned char w)
@@ -207,15 +219,15 @@ static void DownloadFPGA(const char *FpgaImage, int FpgaImageLen, int byterevers
 	}
 
 	if(bytereversal) {
-		/* This is only supported for DWORD aligned images */
-		if( ((int)FpgaImage % sizeof(DWORD)) == 0 ) {
+		/* This is only supported for uint32_t aligned images */
+		if( ((int)FpgaImage % sizeof(uint32_t)) == 0 ) {
 			i=0;
 			while(FpgaImageLen-->0)
 				DownloadFPGA_byte(FpgaImage[(i++)^0x3]);
-			/* Explanation of the magic in the above line: 
+			/* Explanation of the magic in the above line:
 			 * i^0x3 inverts the lower two bits of the integer i, counting backwards
 			 * for each 4 byte increment. The generated sequence of (i++)^3 is
-			 * 3 2 1 0 7 6 5 4 11 10 9 8 15 14 13 12 etc. pp. 
+			 * 3 2 1 0 7 6 5 4 11 10 9 8 15 14 13 12 etc. pp.
 			 */
 		}
 	} else {
@@ -240,7 +252,7 @@ static void DownloadFPGA(const char *FpgaImage, int FpgaImageLen, int byterevers
 
 static char *bitparse_headers_start;
 static char *bitparse_bitstream_end;
-static int bitparse_initialized;
+static int bitparse_initialized = 0;
 /* Simple Xilinx .bit parser. The file starts with the fixed opaque byte sequence
  * 00 09 0f f0 0f f0 0f f0 0f f0 00 00 01
  * After that the format is 1 byte section type (ASCII character), 2 byte length
@@ -251,7 +263,7 @@ static const char _bitparse_fixed_header[] = {0x00, 0x09, 0x0f, 0xf0, 0x0f, 0xf0
 static int bitparse_init(void * start_address, void *end_address)
 {
 	bitparse_initialized = 0;
-	
+
 	if(memcmp(_bitparse_fixed_header, start_address, sizeof(_bitparse_fixed_header)) != 0) {
 		return 0; /* Not matched */
 	} else {
@@ -286,12 +298,12 @@ int bitparse_find_section(char section_name, char **section_start, unsigned int
 			current_length += (*pos++) << 8;
 			current_length += (*pos++) << 0;
 		}
-		
+
 		if(current_name != 'e' && current_length > 255) {
 			/* Maybe a parse error */
 			break;
 		}
-		
+
 		if(current_name == section_name) {
 			/* Found it */
 			*section_start = pos;
@@ -299,10 +311,10 @@ int bitparse_find_section(char section_name, char **section_start, unsigned int
 			result = 1;
 			break;
 		}
-		
+
 		pos += current_length; /* Skip section */
 	}
-	
+
 	return result;
 }
 
@@ -310,12 +322,28 @@ int bitparse_find_section(char section_name, char **section_start, unsigned int
 // Find out which FPGA image format is stored in flash, then call DownloadFPGA
 // with the right parameters to download the image
 //-----------------------------------------------------------------------------
-extern char _binary_fpga_bit_start, _binary_fpga_bit_end;
-void FpgaDownloadAndGo(void)
+extern char _binary_fpga_lf_bit_start, _binary_fpga_lf_bit_end;
+extern char _binary_fpga_hf_bit_start, _binary_fpga_hf_bit_end;
+void FpgaDownloadAndGo(int bitstream_version)
 {
+	void *bit_start;
+	void *bit_end;
+
+	// check whether or not the bitstream is already loaded
+	if (FpgaGatherBitstreamVersion() == bitstream_version)
+		return;
+
+	if (bitstream_version == FPGA_BITSTREAM_LF) {
+		bit_start = &_binary_fpga_lf_bit_start;
+		bit_end = &_binary_fpga_lf_bit_end;
+	} else if (bitstream_version == FPGA_BITSTREAM_HF) {
+		bit_start = &_binary_fpga_hf_bit_start;
+		bit_end = &_binary_fpga_hf_bit_end;
+	} else
+		return;
 	/* Check for the new flash image format: Should have the .bit file at &_binary_fpga_bit_start
 	 */
-	if(bitparse_init(&_binary_fpga_bit_start, &_binary_fpga_bit_end)) {
+	if(bitparse_init(bit_start, bit_end)) {
 		/* Successfully initialized the .bit parser. Find the 'e' section and
 		 * send its contents to the FPGA.
 		 */
@@ -323,37 +351,50 @@ void FpgaDownloadAndGo(void)
 		unsigned int bitstream_length;
 		if(bitparse_find_section('e', &bitstream_start, &bitstream_length)) {
 			DownloadFPGA(bitstream_start, bitstream_length, 0);
-			
+
 			return; /* All done */
 		}
 	}
-	
+
 	/* Fallback for the old flash image format: Check for the magic marker 0xFFFFFFFF
-	 * 0xAA995566 at address 0x102000. This is raw bitstream with a size of 336,768 bits 
-	 * = 10,524 DWORDs, stored as DWORDS e.g. little-endian in memory, but each DWORD
+	 * 0xAA995566 at address 0x102000. This is raw bitstream with a size of 336,768 bits
+	 * = 10,524 uint32_t, stored as uint32_t e.g. little-endian in memory, but each DWORD
 	 * is still to be transmitted in MSBit first order. Set the invert flag to indicate
 	 * that the DownloadFPGA function should invert every 4 byte sequence when doing
 	 * the bytewise download.
 	 */
-	if( *(DWORD*)0x102000 == 0xFFFFFFFF && *(DWORD*)0x102004 == 0xAA995566 )
+	if( *(uint32_t*)0x102000 == 0xFFFFFFFF && *(uint32_t*)0x102004 == 0xAA995566 )
 		DownloadFPGA((char*)0x102000, 10524*4, 1);
 }
 
+int FpgaGatherBitstreamVersion()
+{
+	char temp[256];
+	FpgaGatherVersion(temp, sizeof (temp));
+	if (!memcmp("LF", temp, 2))
+		return FPGA_BITSTREAM_LF;
+	else if (!memcmp("HF", temp, 2))
+		return FPGA_BITSTREAM_HF;
+	return FPGA_BITSTREAM_ERR;
+}
+
 void FpgaGatherVersion(char *dst, int len)
 {
-	char *fpga_info; 
+	char *fpga_info;
 	unsigned int fpga_info_len;
 	dst[0] = 0;
 	if(!bitparse_find_section('e', &fpga_info, &fpga_info_len)) {
 		strncat(dst, "FPGA image: legacy image without version information", len-1);
 	} else {
-		strncat(dst, "FPGA image built", len-1);
 		/* USB packets only have 48 bytes data payload, so be terse */
-#if 0
 		if(bitparse_find_section('a', &fpga_info, &fpga_info_len) && fpga_info[fpga_info_len-1] == 0 ) {
-			strncat(dst, " from ", len-1);
-			strncat(dst, fpga_info, len-1);
+			if (!memcmp("fpga_lf", fpga_info, 7))
+				strncat(dst, "LF ", len-1);
+			else if (!memcmp("fpga_hf", fpga_info, 7))
+				strncat(dst, "HF ", len-1);
 		}
+		strncat(dst, "FPGA image built", len-1);
+#if 0
 		if(bitparse_find_section('b', &fpga_info, &fpga_info_len) && fpga_info[fpga_info_len-1] == 0 ) {
 			strncat(dst, " for ", len-1);
 			strncat(dst, fpga_info, len-1);
@@ -375,7 +416,7 @@ void FpgaGatherVersion(char *dst, int len)
 // The bit format is:  C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
 // where C is the 4 bit command and D is the 12 bit data
 //-----------------------------------------------------------------------------
-void FpgaSendCommand(WORD cmd, WORD v)
+void FpgaSendCommand(uint16_t cmd, uint16_t v)
 {
 	SetupSpi(SPI_FPGA_MODE);
 	while ((AT91C_BASE_SPI->SPI_SR & AT91C_SPI_TXEMPTY) == 0);		// wait for the transfer to complete
@@ -386,7 +427,7 @@ void FpgaSendCommand(WORD cmd, WORD v)
 // vs. clone vs. etc.). This is now a special case of FpgaSendCommand() to
 // avoid changing this function's occurence everywhere in the source code.
 //-----------------------------------------------------------------------------
-void FpgaWriteConfWord(BYTE v)
+void FpgaWriteConfWord(uint8_t v)
 {
 	FpgaSendCommand(FPGA_CMD_SET_CONFREG, v);
 }
@@ -396,7 +437,7 @@ void FpgaWriteConfWord(BYTE v)
 // closable, but should only close one at a time. Not an FPGA thing, but
 // the samples from the ADC always flow through the FPGA.
 //-----------------------------------------------------------------------------
-void SetAdcMuxFor(DWORD whichGpio)
+void SetAdcMuxFor(uint32_t whichGpio)
 {
 	AT91C_BASE_PIOA->PIO_OER =
 		GPIO_MUXSEL_HIPKD |