X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/proxmark3-svn/blobdiff_plain/2abdfa491ccf46320cd813764ca8ca49073388ed..8085377413257aa75a43540f40697ed9273d06a1:/armsrc/util.c

diff --git a/armsrc/util.c b/armsrc/util.c
index 2ad3570c..120e7b44 100644
--- a/armsrc/util.c
+++ b/armsrc/util.c
@@ -14,24 +14,26 @@
 #include "apps.h"
 #include "BigBuf.h"
 
-
-
 void print_result(char *name, uint8_t *buf, size_t len) {
-   uint8_t *p = buf;
+	uint8_t *p = buf;
 
-   if ( len % 16 == 0 ) {
-	   for(; p-buf < len; p += 16)
-       Dbprintf("[%s:%d/%d] %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
+	if ( len % 16 == 0 ) {
+		for(; p-buf < len; p += 16)
+			Dbprintf("[%s:%d/%d] %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
 				name,
 				p-buf,
 				len,
 				p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7],p[8], p[9], p[10], p[11], p[12], p[13], p[14], p[15]
-	   );
-   }
-   else {
-   for(; p-buf < len; p += 8)
-       Dbprintf("[%s:%d/%d] %02x %02x %02x %02x %02x %02x %02x %02x", name, p-buf, len, p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]);
-   }
+			);
+	}
+	else {
+		for(; p-buf < len; p += 8)
+			Dbprintf("[%s:%d/%d] %02x %02x %02x %02x %02x %02x %02x %02x",
+				name,
+				p-buf,
+				len,
+				p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]);
+	}
 }
 
 size_t nbytes(size_t nbits) {
@@ -46,16 +48,14 @@ uint32_t SwapBits(uint32_t value, int nrbits) {
 	return newvalue;
 }
 
-void num_to_bytes(uint64_t n, size_t len, uint8_t* dest)
-{
+void num_to_bytes(uint64_t n, size_t len, uint8_t* dest) {
 	while (len--) {
 		dest[len] = (uint8_t) n;
 		n >>= 8;
 	}
 }
 
-uint64_t bytes_to_num(uint8_t* src, size_t len)
-{
+uint64_t bytes_to_num(uint8_t* src, size_t len) {
 	uint64_t num = 0;
 	while (len--) {
 		num = (num << 8) | (*src);
@@ -65,7 +65,7 @@ uint64_t bytes_to_num(uint8_t* src, size_t len)
 }
 
 // RotateLeft - Ultralight, Desfire
-void rol(uint8_t *data, const size_t len){
+void rol(uint8_t *data, const size_t len) {
     uint8_t first = data[0];
     for (size_t i = 0; i < len-1; i++) {
         data[i] = data[i+1];
@@ -346,17 +346,18 @@ void StartCountUS()
 uint32_t RAMFUNC GetCountUS(){
 	//return (AT91C_BASE_TC1->TC_CV * 0x8000) + ((AT91C_BASE_TC0->TC_CV / 15) * 10);
 	//  By suggestion from PwPiwi, http://www.proxmark.org/forum/viewtopic.php?pid=17548#p17548
-	return (AT91C_BASE_TC1->TC_CV * 0x8000) + ((AT91C_BASE_TC0->TC_CV * 2) / 3); 
+	//return (AT91C_BASE_TC1->TC_CV * 0x8000) + ((AT91C_BASE_TC0->TC_CV * 2) / 3); 
+	return (AT91C_BASE_TC1->TC_CV * 0x8000) + ((AT91C_BASE_TC0->TC_CV << 1) / 3); 
 }
 
-static uint32_t GlobalUsCounter = 0;
+// static uint32_t GlobalUsCounter = 0;
 
-uint32_t RAMFUNC GetDeltaCountUS(){
-	uint32_t g_cnt = GetCountUS();
-	uint32_t g_res = g_cnt - GlobalUsCounter;
-	GlobalUsCounter = g_cnt;
-	return g_res;
-}
+// uint32_t RAMFUNC GetDeltaCountUS(){
+	// uint32_t g_cnt = GetCountUS();
+	// uint32_t g_res = g_cnt - GlobalUsCounter;
+	// GlobalUsCounter = g_cnt;
+	// return g_res;
+// }
 
 
 //  -------------------------------------------------------------------------
@@ -397,17 +398,17 @@ void StartCountSspClk()
 	AT91C_BASE_TC2->TC_CMR = AT91C_TC_CLKS_XC2	 			// TC2 clock = XC2 clock = TIOA0
 							| AT91C_TC_WAVE 				// Waveform Mode
 							| AT91C_TC_WAVESEL_UP;	 		// just count
-	
+
 	AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN;				// enable TC0
 	AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN;				// enable TC1
 	AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKEN;				// enable TC2
 
-	//
-	// synchronize the counter with the ssp_frame signal. Note: FPGA must be in any iso14446 mode, otherwise the frame signal would not be present 
-	//
+	// synchronize the counter with the ssp_frame signal. 
+	// Note: FPGA must be in any iso14443 mode, otherwise the frame signal would not be present 
 	while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME)); 	// wait for ssp_frame to go high (start of frame)
 	while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME); 		// wait for ssp_frame to be low
 	while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)); 	// wait for ssp_clk to go high
+
 	// note: up to now two ssp_clk rising edges have passed since the rising edge of ssp_frame
 	// it is now safe to assert a sync signal. This sets all timers to 0 on next active clock edge
 	AT91C_BASE_TCB->TCB_BCR = 1;							// assert Sync (set all timers to 0 on next active clock edge)
@@ -415,8 +416,9 @@ void StartCountSspClk()
 	// at the next (4th) ssp_clk rising edge, TC0 (the low word of our counter) will be reset. From now on,
 	// whenever the last three bits of our counter go 0, we can be sure to be in the middle of a frame transfer.
 	// (just started with the transfer of the 4th Bit).
-	// The high word of the counter (TC2) will not reset until the low word (TC0) overflows. Therefore need to wait quite some time before
-	// we can use the counter.
+
+	// The high word of the counter (TC2) will not reset until the low word (TC0) overflows. 
+	// Therefore need to wait quite some time before we can use the counter.
 	while (AT91C_BASE_TC0->TC_CV < 0xFFF0);
 }