X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/proxmark3-svn/blobdiff_plain/42c235e7efdac01da7e7ef3e4e442557fe50198d..57e1e31dce70a58da1736b9579a869c1df313a13:/armsrc/lfops.c diff --git a/armsrc/lfops.c b/armsrc/lfops.c index 71d9ba95..ffeb8ea1 100644 --- a/armsrc/lfops.c +++ b/armsrc/lfops.c @@ -43,7 +43,7 @@ void ModThenAcquireRawAdcSamples125k(uint32_t delay_off, uint32_t periods, uint3 uint16_t period_0 = periods >> 16; uint16_t period_1 = periods & 0xFFFF; - // 95 == 125 KHz 88 == 124.8 KHz + // 95 == 125 KHz 88 == 134.8 KHz int divisor_used = (useHighFreq) ? 88 : 95; sample_config sc = { 0,0,1, divisor_used, 0}; setSamplingConfig(&sc); @@ -78,6 +78,8 @@ void ModThenAcquireRawAdcSamples125k(uint32_t delay_off, uint32_t periods, uint3 // now do the read DoAcquisition_config(false); + + FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); } /* blank r/w tag data stream @@ -324,7 +326,6 @@ void AcquireTiType(void) // if not provided a valid crc will be computed from the data and written. void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc) { - StartTicks(); FpgaDownloadAndGo(FPGA_BITSTREAM_LF); if(crc == 0) { crc = update_crc16(crc, (idlo)&0xff); @@ -345,8 +346,10 @@ void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc) // whether we're modulating the antenna (high) // or listening to the antenna (low) FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU); + StartTicks(); + LED_A_ON(); - + // steal this pin from the SSP and use it to control the modulation AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT; AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT; @@ -359,7 +362,7 @@ void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc) // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer) // finally end with 0x0300 (write frame) // all data is sent lsb first - // finish with 15ms programming time + // finish with 50ms programming time // modulate antenna HIGH(GPIO_SSC_DOUT); @@ -397,7 +400,8 @@ void SimulateTagLowFrequency(int period, int gap, int ledcontrol) int i = 0; uint8_t *buf = BigBuf_get_addr(); - FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT); + FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU); + //FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT); //FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT | FPGA_LF_EDGE_DETECT_READER_FIELD); //FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT | FPGA_LF_EDGE_DETECT_TOGGLE_MODE ); @@ -418,8 +422,9 @@ void SimulateTagLowFrequency(int period, int gap, int ledcontrol) AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK; // power on antenna - // OPEN_COIL(); - // SpinDelay(50); + OPEN_COIL(); + // charge time + WaitMS(50); for(;;) { WDT_HIT(); @@ -708,7 +713,7 @@ void CmdASKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream) for (i=0; i64){ + if (size == 128){ Dbprintf("EM XL TAG ID: %06x%08x%08x - (%05d_%03d_%08d)", hi, (uint32_t)(lo>>32), @@ -1174,6 +1179,10 @@ void TurnReadLFOn(uint32_t delay) { // Give it a bit of time for the resonant antenna to settle. WaitUS(delay); } +void TurnReadLF_off(uint32_t delay) { + FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); + WaitUS(delay); +} // Write one bit to card void T55xxWriteBit(int bit) { @@ -1386,7 +1395,7 @@ void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT) { data[0] = T55x7_BITRATE_RF_50 | T55x7_MODULATION_FSK2a | last_block << T55x7_MAXBLOCK_SHIFT; //TODO add selection of chip for Q5 or T55x7 - // data[0] = (((50-2)/2)<>1)<>1) << T5555_BITRATE_SHIFT) | T5555_MODULATION_FSK2 | T5555_INVERT_OUTPUT | 2 << T5555_MAXBLOCK_SHIFT; LED_D_ON(); // Program the data blocks for supplied ID @@ -1412,7 +1421,7 @@ void CopyIndala64toT55x7(uint32_t hi, uint32_t lo) { // and the Config for Indala 64 format (RF/32;PSK1 with RF/2;Maxblock=2) uint32_t data[] = { T55x7_BITRATE_RF_32 | T55x7_MODULATION_PSK1 | (2 << T55x7_MAXBLOCK_SHIFT), hi, lo}; //TODO add selection of chip for Q5 or T55x7 - // data[0] = (((32-2)/2)<>1)<>1) << T5555_BITRATE_SHIFT) | T5555_MODULATION_PSK1 | 7 << T5555_MAXBLOCK_SHIFT; WriteT55xx(data, 0, 8); //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data) // T5567WriteBlock(0x603E10E2,0); @@ -1435,7 +1444,7 @@ void CopyIndala224toT55x7(uint32_t uid1, uint32_t uid2, uint32_t uid3, uint32_t void CopyVikingtoT55xx(uint32_t block1, uint32_t block2, uint8_t Q5) { uint32_t data[] = {T55x7_BITRATE_RF_32 | T55x7_MODULATION_MANCHESTER | (2 << T55x7_MAXBLOCK_SHIFT), block1, block2}; //t5555 (Q5) BITRATE = (RF-2)/2 (iceman) - if (Q5) data[0] = (32 << T5555_BITRATE_SHIFT) | T5555_MODULATION_MANCHESTER | 2 << T5555_MAXBLOCK_SHIFT; + if (Q5) data[0] = (((32-2)>>1) << T5555_BITRATE_SHIFT) | T5555_MODULATION_MANCHESTER | 2 << T5555_MAXBLOCK_SHIFT; // Program the data blocks for supplied ID and the block 0 config WriteT55xx(data, 0, 3); LED_D_OFF(); @@ -1519,8 +1528,8 @@ void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo) { } data[0] = clock | T55x7_MODULATION_MANCHESTER | (2 << T55x7_MAXBLOCK_SHIFT); } else { //t5555 (Q5) - clock = (clock-2)>>1; //n = (RF-2)/2 - data[0] = (clock << T5555_BITRATE_SHIFT) | T5555_MODULATION_MANCHESTER | (2 << T5555_MAXBLOCK_SHIFT); + // t5555 (Q5) BITRATE = (RF-2)/2 (iceman) + data[0] = ( ((clock-2) >> 1) << T5555_BITRATE_SHIFT) | T5555_MODULATION_MANCHESTER | (2 << T5555_MAXBLOCK_SHIFT); } WriteT55xx(data, 0, 3); @@ -1535,7 +1544,9 @@ void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo) { //----------------------------------- // EM4469 / EM4305 routines //----------------------------------- -#define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored +// Below given command set. +// Commands are including the even parity, binary mirrored +#define FWD_CMD_LOGIN 0xC #define FWD_CMD_WRITE 0xA #define FWD_CMD_READ 0x9 #define FWD_CMD_DISABLE 0x5 @@ -1584,7 +1595,7 @@ uint8_t Prepare_Addr( uint8_t addr ) { uint8_t i; line_parity = 0; - for(i=0;i<6;i++) { + for( i=0; i<6; i++ ) { *forward_ptr++ = addr; line_parity ^= addr; addr >>= 1; @@ -1638,102 +1649,180 @@ uint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) { //==================================================================== void SendForward(uint8_t fwd_bit_count) { +// iceman, 21.3us increments for the USclock verification. +// 55FC * 8us == 440us / 21.3 === 20.65 steps. could be too short. Go for 56FC instead +// 32FC * 8us == 256us / 21.3 == 12.018 steps. ok +// 16FC * 8us == 128us / 21.3 == 6.009 steps. ok +#ifndef EM_START_GAP +#define EM_START_GAP 55*8 +#endif + fwd_write_ptr = forwardLink_data; fwd_bit_sz = fwd_bit_count; - LED_D_ON(); - // Set up FPGA, 125kHz LFSetupFPGAForADC(95, true); // force 1st mod pulse (start gap must be longer for 4305) fwd_bit_sz--; //prepare next bit modulation fwd_write_ptr++; - FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off - WaitUS(55*8); //55 cycles off (8us each)for 4305 // ICEMAN: problem with (us) clock is 21.3us increments - FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on - WaitUS(16*8); //16 cycles on (8us each) // ICEMAN: problem with (us) clock is 21.3us increments + + TurnReadLF_off(EM_START_GAP); + TurnReadLFOn(18*8); - // now start writting + // now start writting with bitbanging the antenna. while(fwd_bit_sz-- > 0) { //prepare next bit modulation - if(((*fwd_write_ptr++) & 1) == 1) - WaitUS(32*8); //32 cycles at 125Khz (8us each) // ICEMAN: problem with (us) clock is 21.3us increments - else { - //These timings work for 4469/4269/4305 (with the 55*8 above) - FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off - WaitUS(16*8); //16-4 cycles off (8us each) // ICEMAN: problem with (us) clock is 21.3us increments - FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on - WaitUS(16*8); //16 cycles on (8us each) // ICEMAN: problem with (us) clock is 21.3us increments + if(((*fwd_write_ptr++) & 1) == 1) { + WaitUS(32); + } else { + TurnReadLF_off(23*8); + TurnReadLFOn(16*8); } } } -void EM4xLogin(uint32_t Password) { - - uint8_t fwd_bit_count; +void EM4xLogin(uint32_t pwd) { + uint8_t len; forward_ptr = forwardLink_data; - fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN ); - fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 ); - SendForward(fwd_bit_count); - - //Wait for command to complete - WaitMS(20); + len = Prepare_Cmd( FWD_CMD_LOGIN ); + len += Prepare_Data( pwd & 0xFFFF, pwd >> 16 ); + SendForward(len); + //WaitUS(20); // no wait for login command. + // should receive + // 0000 1010 ok. + // 0000 0001 fail } -void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) { - - uint8_t fwd_bit_count; - uint8_t *dest = BigBuf_get_addr(); - uint16_t bufsize = BigBuf_max_traceLen(); // ICEMAN: this tries to fill up all tracelog space - uint32_t i = 0; +void EM4xReadWord(uint8_t addr, uint32_t pwd, uint8_t usepwd) { - // Clear destination buffer before sending the command + LED_A_ON(); + uint8_t len; + + //clear buffer now so it does not interfere with timing later BigBuf_Clear_ext(false); - //If password mode do login - if (PwdMode == 1) EM4xLogin(Pwd); + /* should we read answer from Logincommand? + * + * should receive + * 0000 1010 ok. + * 0000 0001 fail + **/ + if (usepwd) EM4xLogin(pwd); forward_ptr = forwardLink_data; - fwd_bit_count = Prepare_Cmd( FWD_CMD_READ ); - fwd_bit_count += Prepare_Addr( Address ); + len = Prepare_Cmd( FWD_CMD_READ ); + len += Prepare_Addr( addr ); - SendForward(fwd_bit_count); + SendForward(len); - // Now do the acquisition - // ICEMAN, change to the one in lfsampling.c - i = 0; - for(;;) { - if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) { - AT91C_BASE_SSC->SSC_THR = 0x43; - } - if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) { - dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR; - ++i; - if (i >= bufsize) break; - } - } + WaitUS(400); - FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off + DoPartialAcquisition(20, true, 6000); + + FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); cmd_send(CMD_ACK,0,0,0,0,0); - LED_D_OFF(); + LED_A_OFF(); } -void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) { +void EM4xWriteWord(uint32_t flag, uint32_t data, uint32_t pwd) { - uint8_t fwd_bit_count; + LED_A_ON(); + + bool usePwd = (flag & 0xF); + uint8_t addr = (flag >> 8) & 0xFF; + uint8_t len; + + //clear buffer now so it does not interfere with timing later + BigBuf_Clear_ext(false); - //If password mode do login - if (PwdMode == 1) EM4xLogin(Pwd); + /* should we read answer from Logincommand? + * + * should receive + * 0000 1010 ok. + * 0000 0001 fail + **/ + if (usePwd) EM4xLogin(pwd); forward_ptr = forwardLink_data; - fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE ); - fwd_bit_count += Prepare_Addr( Address ); - fwd_bit_count += Prepare_Data( Data&0xFFFF, Data>>16 ); + len = Prepare_Cmd( FWD_CMD_WRITE ); + len += Prepare_Addr( addr ); + len += Prepare_Data( data & 0xFFFF, data >> 16 ); + + SendForward(len); + + //Wait 20ms for write to complete? + WaitMS(7); + + //Capture response if one exists + DoPartialAcquisition(20, true, 6000); + + FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); + cmd_send(CMD_ACK,0,0,0,0,0); + LED_A_OFF(); +} + +/* +Reading a COTAG. + +COTAG needs the reader to send a startsequence and the card has an extreme slow datarate. +because of this, we can "sample" the data signal but we interpreate it to Manchester direct. + +READER START SEQUENCE: +burst 800 us, gap 2.2 msecs +burst 3.6 msecs gap 2.2 msecs +burst 800 us gap 2.2 msecs +pulse 3.6 msecs + +This triggers a COTAG tag to response +*/ +void Cotag(uint32_t arg0) { +#ifndef OFF +# define OFF { FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); WaitUS(2035); } +#endif +#ifndef ON +# define ON(x) { FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD); WaitUS((x)); } +#endif + uint8_t rawsignal = arg0 & 0xF; + + LED_A_ON(); - SendForward(fwd_bit_count); + // Switching to LF image on FPGA. This might empty BigBuff + FpgaDownloadAndGo(FPGA_BITSTREAM_LF); + + //clear buffer now so it does not interfere with timing later + BigBuf_Clear_ext(false); + + // Set up FPGA, 132kHz to power up the tag + FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 89); + FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD); - //Wait for write to complete - WaitMS(20); + // Connect the A/D to the peak-detected low-frequency path. + SetAdcMuxFor(GPIO_MUXSEL_LOPKD); + + // Now set up the SSC to get the ADC samples that are now streaming at us. + FpgaSetupSsc(); + + // start clock - 1.5ticks is 1us + StartTicks(); + + //send COTAG start pulse + ON(740) OFF + ON(3330) OFF + ON(740) OFF + ON(1000) + + switch(rawsignal) { + case 0: doCotagAcquisition(50000); break; + case 1: doCotagAcquisitionManchester(); break; + case 2: DoAcquisition_config(TRUE); break; + } + + // Turn the field off FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off - LED_D_OFF(); + cmd_send(CMD_ACK,0,0,0,0,0); + LED_A_OFF(); } + +/* +* EM4305 support +*/