X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/proxmark3-svn/blobdiff_plain/539fd59ebe7f3ed79a7d9327d4499aa42fd47382..57e1e31dce70a58da1736b9579a869c1df313a13:/armsrc/legicrf.c diff --git a/armsrc/legicrf.c b/armsrc/legicrf.c index 9abc7761..f58cb442 100644 --- a/armsrc/legicrf.c +++ b/armsrc/legicrf.c @@ -69,7 +69,7 @@ static void setup_timer(void) { */ // At TIMER_CLOCK3 (MCK/32) -// testing calculating in (us) microseconds. +// testing calculating in ticks. 1.5ticks = 1us #define RWD_TIME_1 120 // READER_TIME_PAUSE 20us off, 80us on = 100us 80 * 1.5 == 120ticks #define RWD_TIME_0 60 // READER_TIME_PAUSE 20us off, 40us on = 60us 40 * 1.5 == 60ticks #define RWD_TIME_PAUSE 30 // 20us == 20 * 1.5 == 30ticks */ @@ -180,7 +180,7 @@ void frame_send_tag(uint16_t response, uint8_t bits) { AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT; /* TAG_FRAME_WAIT -> shift by 2 */ - legic_prng_forward(2); + legic_prng_forward(3); response ^= legic_prng_get_bits(bits); /* Wait for the frame start */ @@ -297,19 +297,18 @@ static void frame_receiveAsReader(struct legic_frame * const f, uint8_t bits) { // Setup pm3 as a Legic Reader static uint32_t setup_phase_reader(uint8_t iv) { - // Switch on carrier and let the tag charge for 1ms + // Switch on carrier and let the tag charge for 5ms HIGH(GPIO_SSC_DOUT); - WaitUS(5000); + WaitUS(5000); ResetTicks(); - // no keystream yet legic_prng_init(0); // send IV handshake frame_sendAsReader(iv, 7); - // Now both tag and reader has same IV. Prng can start. + // tag and reader has same IV. legic_prng_init(iv); frame_receiveAsReader(¤t_frame, 6); @@ -333,7 +332,7 @@ static uint32_t setup_phase_reader(uint8_t iv) { return current_frame.data; } -static void LegicCommonInit(void) { +void LegicCommonInit(bool clear_mem) { FpgaDownloadAndGo(FPGA_BITSTREAM_HF); FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX); @@ -347,7 +346,8 @@ static void LegicCommonInit(void) { // reserve a cardmem, meaning we can use the tracelog function in bigbuff easier. cardmem = BigBuf_get_EM_addr(); - memset(cardmem, 0x00, LEGIC_CARD_MEMSIZE); + if ( clear_mem ) + memset(cardmem, 0x00, LEGIC_CARD_MEMSIZE); clear_trace(); set_tracing(TRUE); @@ -470,7 +470,7 @@ int LegicRfReader(uint16_t offset, uint16_t len, uint8_t iv) { uint8_t isOK = 1; legic_card_select_t card; - LegicCommonInit(); + LegicCommonInit(TRUE); if ( legic_select_card_iv(&card, iv) ) { isOK = 0; @@ -513,7 +513,7 @@ void LegicRfWriter(uint16_t offset, uint16_t len, uint8_t iv, uint8_t *data) { goto OUT; } - LegicCommonInit(); + LegicCommonInit(TRUE); if ( legic_select_card_iv(&card, iv) ) { isOK = 0; @@ -613,7 +613,7 @@ void LegicRfInfo(void){ uint8_t buf[sizeof(legic_card_select_t)] = {0x00}; legic_card_select_t *card = (legic_card_select_t*) buf; - LegicCommonInit(); + LegicCommonInit(FALSE); if ( legic_select_card(card) ) { cmd_send(CMD_ACK,0,0,0,0,0); @@ -654,31 +654,35 @@ static void frame_handle_tag(struct legic_frame const * const f) // log //uint8_t cmdbytes[] = {bits, BYTEx(data, 0), BYTEx(data, 1)}; //LogTrace(cmdbytes, sizeof(cmdbytes), starttime, GET_TICKS, NULL, FALSE); - - cardmem = BigBuf_get_EM_addr(); - + //Dbprintf("ICE: enter frame_handle_tag: %02x ", f->bits); + /* First Part of Handshake (IV) */ if(f->bits == 7) { LED_C_ON(); // Reset prng timer - ResetTimer(prng_timer); + //ResetTimer(prng_timer); + ResetTicks(); // IV from reader. legic_prng_init(f->data); + Dbprintf("ICE: IV: %02x ", f->data); + // We should have three tagtypes with three different answers. - frame_send_tag(0x3d, 6); /* 0x3d^0x26 = 0x1B */ + legic_prng_forward(2); + //frame_send_tag(0x3d, 6); /* MIM1024 0x3d^0x26 = 0x1B */ + frame_send_tag(0x1d, 6); // MIM256 legic_state = STATE_IV; legic_read_count = 0; legic_prng_bc = 0; legic_prng_iv = f->data; - - ResetTimer(timer); - WaitUS(280); + //ResetTimer(timer); + //WaitUS(280); + WaitTicks(388); return; } @@ -690,7 +694,7 @@ static void frame_handle_tag(struct legic_frame const * const f) legic_state = STATE_CON; ResetTimer(timer); - WaitUS(200); + WaitTicks(300); return; } else { @@ -708,13 +712,14 @@ static void frame_handle_tag(struct legic_frame const * const f) uint16_t addr = f->data ^ key; addr >>= 1; uint8_t data = cardmem[addr]; - int hash = legic4Crc(LEGIC_READ, addr, data, 11) << 8; + + uint32_t crc = legic4Crc(LEGIC_READ, addr, data, 11) << 8; - legic_read_count++; - legic_prng_forward(legic_reqresp_drift); + //legic_read_count++; + //legic_prng_forward(legic_reqresp_drift); - frame_send_tag(hash | data, 12); - ResetTimer(timer); + frame_send_tag(crc | data, 12); + //ResetTimer(timer); legic_prng_forward(2); WaitTicks(330); return; @@ -745,11 +750,11 @@ static void frame_handle_tag(struct legic_frame const * const f) Dbprintf("IV: %03.3x", legic_prng_iv); } - legic_state = STATE_DISCON; - legic_read_count = 0; - SpinDelay(10); - LED_C_OFF(); - return; + legic_state = STATE_DISCON; + legic_read_count = 0; + WaitMS(10); + LED_C_OFF(); + return; } /* Read bit by bit untill full frame is received @@ -790,18 +795,37 @@ void LegicRfSimulate(int phase, int frame, int reqresp) */ int old_level = 0, active = 0; + volatile int32_t level = 0; + legic_state = STATE_DISCON; - legic_phase_drift = phase; legic_frame_drift = frame; legic_reqresp_drift = reqresp; + + /* to get the stream of bits from FPGA in sim mode.*/ FpgaDownloadAndGo(FPGA_BITSTREAM_HF); + // Set up the synchronous serial port + //FpgaSetupSsc(); + // connect Demodulated Signal to ADC: SetAdcMuxFor(GPIO_MUXSEL_HIPKD); FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_MODULATE_212K); + //FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_NO_MODULATION); + #define LEGIC_DMA_BUFFER 256 + // The DMA buffer, used to stream samples from the FPGA + //uint8_t *dmaBuf = BigBuf_malloc(LEGIC_DMA_BUFFER); + //uint8_t *data = dmaBuf; + // Setup and start DMA. + // if ( !FpgaSetupSscDma((uint8_t*) dmaBuf, LEGIC_DMA_BUFFER) ){ + // if (MF_DBGLEVEL > 1) Dbprintf("FpgaSetupSscDma failed. Exiting"); + // return; + // } + + //StartCountSspClk(); /* Bitbang the receiver */ - LINE_IN; + AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_DIN; + AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DIN; // need a way to determine which tagtype we are simulating @@ -817,30 +841,62 @@ void LegicRfSimulate(int phase, int frame, int reqresp) LED_B_ON(); DbpString("Starting Legic emulator, press button to end"); - + + /* + * The mode FPGA_HF_SIMULATOR_MODULATE_212K works like this. + * - A 1-bit input to the FPGA becomes 8 pulses on 212kHz (fc/64) (18.88us). + * - A 0-bit input to the FPGA becomes an unmodulated time of 18.88us + * + * In this mode the SOF can be written as 00011101 = 0x1D + * The EOF can be written as 10111000 = 0xb8 + * A logic 1 is 01 + * A logic 0 is 10 + volatile uint8_t b; + uint8_t i = 0; + while( !BUTTON_PRESS() ) { + WDT_HIT(); + + // not sending anything. + if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) { + AT91C_BASE_SSC->SSC_THR = 0x00; + } + + // receive + if ( AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY ) { + b = (uint8_t) AT91C_BASE_SSC->SSC_RHR; + bd[i] = b; + ++i; + // if(OutOfNDecoding(b & 0x0f)) + // *len = Uart.byteCnt; + } + + } + */ + while(!BUTTON_PRESS() && !usb_poll_validate_length()) { - volatile uint32_t level = !!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN); + + level = !!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN); uint32_t time = GET_TICKS; if (level != old_level) { - - if (level) { + if (level == 1) { - ResetTicks(); - + //Dbprintf("start, %u ", time); + StartTicks(); + // did we get a signal if (FUZZ_EQUAL(time, RWD_TIME_1, RWD_TIME_FUZZ)) { - /* 1 bit */ + // 1 bit emit(1); active = 1; LED_A_ON(); } else if (FUZZ_EQUAL(time, RWD_TIME_0, RWD_TIME_FUZZ)) { - /* 0 bit */ + // 0 bit emit(0); active = 1; LED_A_ON(); } else if (active) { - /* invalid */ + // invalid emit(-1); active = 0; LED_A_OFF(); @@ -848,8 +904,9 @@ void LegicRfSimulate(int phase, int frame, int reqresp) } } + /* Frame end */ - if(time >= (RWD_TIME_1+RWD_TIME_FUZZ) && active) { + if(time >= (RWD_TIME_1 + RWD_TIME_FUZZ) && active) { emit(-1); active = 0; LED_A_OFF(); @@ -860,19 +917,23 @@ void LegicRfSimulate(int phase, int frame, int reqresp) * shutdown in its status register. Reading the SR has the * side-effect of clearing any pending state in there. */ - if(time >= (20*RWD_TIME_1) && (timer->TC_SR & AT91C_TC_CLKSTA)) + //if(time >= (20*RWD_TIME_1) && (timer->TC_SR & AT91C_TC_CLKSTA)) + if(time >= (20 * RWD_TIME_1) ) StopTicks(); old_level = level; WDT_HIT(); - } +} WDT_HIT(); + DbpString("LEGIC Prime emulator stopped"); switch_off_tag_rwd(); + FpgaDisableSscDma(); LEDsoff(); cmd_send(CMD_ACK, 1, 0, 0, 0, 0); } + //----------------------------------------------------------------------------- // Code up a string of octets at layer 2 (including CRC, we don't generate // that here) so that they can be transmitted to the reader. Doesn't transmit