X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/proxmark3-svn/blobdiff_plain/6658905f18a1eebc148836f26c731dea9c1377dc..269a820f9e9eed1ce34f39e9eb2b5df399a31bdc:/fpga/testbed_lo_read.v

diff --git a/fpga/testbed_lo_read.v b/fpga/testbed_lo_read.v
index 11908d77..cb0f119c 100644
--- a/fpga/testbed_lo_read.v
+++ b/fpga/testbed_lo_read.v
@@ -1,5 +1,4 @@
 `include "lo_read.v"
-
 /*
 	pck0			- input main 24Mhz clock (PLL / 4)
 	[7:0] adc_d		- input data from A/D converter
@@ -29,6 +28,7 @@ module testbed_lo_read;
 	reg  pck0;
 	reg  [7:0] adc_d;
 	reg  lo_is_125khz;
+	reg [15:0] divisor;
 
 	wire pwr_lo;
 	wire adc_clk;
@@ -37,7 +37,7 @@ module testbed_lo_read;
 	wire ssp_frame;
 	wire ssp_din;
 	wire ssp_clk;
-	wire ssp_dout;
+	reg ssp_dout;
 	wire pwr_hi;
 	wire pwr_oe1;
 	wire pwr_oe2;
@@ -47,7 +47,7 @@ module testbed_lo_read;
 	wire cross_hi;
 	wire dbg;
 
-	lo_read #(5,200) dut(
+	lo_read #(5,10) dut(
 	.pck0(pck0),
 	.ck_1356meg(ck_1356meg),
 	.ck_1356megb(ck_1356megb),
@@ -66,19 +66,20 @@ module testbed_lo_read;
 	.cross_hi(cross_hi),
 	.cross_lo(cross_lo),
 	.dbg(dbg),
-	.lo_is_125khz(lo_is_125khz)
+	.lo_is_125khz(lo_is_125khz),
+	.divisor(divisor)
 	);
 
-	integer idx, i;
+	integer idx, i, adc_val=8;
 
 	// main clock
 	always #5 pck0 = !pck0;
 
-	//new A/D value available from ADC on positive edge
 	task crank_dut;
 	begin
 		@(posedge adc_clk) ;
-		adc_d = $random;
+		adc_d = adc_val;
+		adc_val = (adc_val *2) + 53;
 	end
 	endtask
 
@@ -87,19 +88,14 @@ module testbed_lo_read;
 		// init inputs
 		pck0 = 0;
 		adc_d = 0;
-
-		// simulate 4 A/D cycles at 134Khz
-		lo_is_125khz=0;
-		for (i = 0 ;  i < 4 ;  i = i + 1) begin
-			crank_dut;
-		end
+		ssp_dout = 0;
+		lo_is_125khz = 1;
+		divisor = 255;  //min 16, 95=125Khz, max 255
 
 		// simulate 4 A/D cycles at 125Khz
-		lo_is_125khz=1;
-		for (i = 0 ;  i < 4 ;  i = i + 1) begin
+		for (i = 0 ;  i < 8 ;  i = i + 1) begin
 			crank_dut;
 		end
 		$finish;
 	end
-	
 endmodule // main