X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/proxmark3-svn/blobdiff_plain/6658905f18a1eebc148836f26c731dea9c1377dc..cb366e9dbd0f421c143d6a9f02d7e0abc86c90ba:/fpga/sim.tcl

diff --git a/fpga/sim.tcl b/fpga/sim.tcl
index 477acd1d..0ee8c0c3 100644
--- a/fpga/sim.tcl
+++ b/fpga/sim.tcl
@@ -1,27 +1,27 @@
-#------------------------------------------------------------------------------
-# Run the simulation testbench in ModelSim: recompile both Verilog source
-# files, then start the simulation, add a lot of signals to the waveform
-# viewer, and run. I should (TODO) fix the absolute paths at some point.
-#
-# Jonathan Westhues, Mar 2006
-#------------------------------------------------------------------------------
-
-vlog -work work -O0 C:/depot/proximity/mark3/fpga/fpga.v
-vlog -work work -O0 C:/depot/proximity/mark3/fpga/fpga_tb.v
-
-vsim work.fpga_tb
-
-add wave sim:/fpga_tb/adc_clk
-add wave sim:/fpga_tb/adc_d
-add wave sim:/fpga_tb/pwr_lo
-add wave sim:/fpga_tb/ssp_clk
-add wave sim:/fpga_tb/ssp_frame
-add wave sim:/fpga_tb/ssp_din
-add wave sim:/fpga_tb/ssp_dout
-
-add wave sim:/fpga_tb/dut/clk_lo
-add wave sim:/fpga_tb/dut/pck_divider
-add wave sim:/fpga_tb/dut/carrier_divider_lo
-add wave sim:/fpga_tb/dut/conf_word
-
-run 30000
+#------------------------------------------------------------------------------
+# Run the simulation testbench in ModelSim: recompile both Verilog source
+# files, then start the simulation, add a lot of signals to the waveform
+# viewer, and run. I should (TODO) fix the absolute paths at some point.
+#
+# Jonathan Westhues, Mar 2006
+#------------------------------------------------------------------------------
+
+vlog -work work -O0 C:/depot/proximity/mark3/fpga/fpga.v
+vlog -work work -O0 C:/depot/proximity/mark3/fpga/fpga_tb.v
+
+vsim work.fpga_tb
+
+add wave sim:/fpga_tb/adc_clk
+add wave sim:/fpga_tb/adc_d
+add wave sim:/fpga_tb/pwr_lo
+add wave sim:/fpga_tb/ssp_clk
+add wave sim:/fpga_tb/ssp_frame
+add wave sim:/fpga_tb/ssp_din
+add wave sim:/fpga_tb/ssp_dout
+
+add wave sim:/fpga_tb/dut/clk_lo
+add wave sim:/fpga_tb/dut/pck_divider
+add wave sim:/fpga_tb/dut/carrier_divider_lo
+add wave sim:/fpga_tb/dut/conf_word
+
+run 30000