X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/proxmark3-svn/blobdiff_plain/6fe5fe8d521821b6d9615d9c77031097c94ef50e..b1d615df78a3c258f2568a07fcc4d0d9ca4ab921:/armsrc/lfops.c?ds=sidebyside diff --git a/armsrc/lfops.c b/armsrc/lfops.c index 90b8d0b3..28b8b5df 100644 --- a/armsrc/lfops.c +++ b/armsrc/lfops.c @@ -43,7 +43,7 @@ void ModThenAcquireRawAdcSamples125k(uint32_t delay_off, uint32_t periods, uint3 uint16_t period_0 = periods >> 16; uint16_t period_1 = periods & 0xFFFF; - // 95 == 125 KHz 88 == 124.8 KHz + // 95 == 125 KHz 88 == 134.8 KHz int divisor_used = (useHighFreq) ? 88 : 95; sample_config sc = { 0,0,1, divisor_used, 0}; setSamplingConfig(&sc); @@ -78,6 +78,8 @@ void ModThenAcquireRawAdcSamples125k(uint32_t delay_off, uint32_t periods, uint3 // now do the read DoAcquisition_config(false); + + FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); } /* blank r/w tag data stream @@ -797,7 +799,7 @@ void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol) WDT_HIT(); if (ledcontrol) LED_A_ON(); - DoAcquisition_default(-1,true); + DoAcquisition_default(0, true); // FSK demodulator size = 50*128*2; //big enough to catch 2 sequences of largest format idx = HIDdemodFSK(dest, &size, &hi2, &hi, &lo); @@ -1283,7 +1285,7 @@ void T55xxReadBlock(uint16_t arg0, uint8_t Block, uint32_t Pwd) { // Set up FPGA, 125kHz to power up the tag LFSetupFPGAForADC(95, true); - SpinDelay(3); + //SpinDelay(3); // Trigger T55x7 Direct Access Mode with start gap FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); @@ -1310,7 +1312,7 @@ void T55xxReadBlock(uint16_t arg0, uint8_t Block, uint32_t Pwd) { TurnReadLFOn(READ_GAP); // Acquisition - doT55x7Acquisition(12000); + doT55x7Acquisition(7679); // Turn the field off FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off @@ -1369,7 +1371,7 @@ void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT) { data[4] = manchesterEncode2Bytes(hi & 0xFFFF); data[5] = manchesterEncode2Bytes(lo >> 16); data[6] = manchesterEncode2Bytes(lo & 0xFFFF); - } else { + } else { // Ensure no more than 44 bits supplied if (hi > 0xFFF) { DbpString("Tags can only have 44 bits."); @@ -1389,13 +1391,8 @@ void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT) { // data[0] = (((50-2)/2)<>= 1; @@ -1646,102 +1642,171 @@ uint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) { //==================================================================== void SendForward(uint8_t fwd_bit_count) { +// iceman, 21.3us increments for the USclock verification. +// 55FC * 8us == 440us / 21.3 === 20.65 steps. could be too short. Go for 56FC instead +// 32FC * 8us == 256us / 21.3 == 12.018 steps. ok +// 16FC * 8us == 128us / 21.3 == 6.009 steps. ok + +#ifndef EM_START_GAP +#define EM_START_GAP 56*8 +#endif +#ifndef EM_ONE_GAP +#define EM_ONE_GAP 32*8 +#endif +#ifndef EM_ZERO_GAP +# define EM_ZERO_GAP 16*8 +#endif + fwd_write_ptr = forwardLink_data; fwd_bit_sz = fwd_bit_count; - LED_D_ON(); - // Set up FPGA, 125kHz LFSetupFPGAForADC(95, true); // force 1st mod pulse (start gap must be longer for 4305) fwd_bit_sz--; //prepare next bit modulation fwd_write_ptr++; - FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off - WaitUS(55*8); //55 cycles off (8us each)for 4305 // ICEMAN: problem with (us) clock is 21.3us increments - FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on - WaitUS(16*8); //16 cycles on (8us each) // ICEMAN: problem with (us) clock is 21.3us increments + + FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); + WaitUS(EM_START_GAP); - // now start writting + TurnReadLFOn(EM_ZERO_GAP); + + // now start writting with bitbanging the antenna. while(fwd_bit_sz-- > 0) { //prepare next bit modulation if(((*fwd_write_ptr++) & 1) == 1) - WaitUS(32*8); //32 cycles at 125Khz (8us each) // ICEMAN: problem with (us) clock is 21.3us increments + WaitUS(EM_ONE_GAP); else { - //These timings work for 4469/4269/4305 (with the 55*8 above) - FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off - WaitUS(16*8); //16-4 cycles off (8us each) // ICEMAN: problem with (us) clock is 21.3us increments - FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on - WaitUS(16*8); //16 cycles on (8us each) // ICEMAN: problem with (us) clock is 21.3us increments + //These timings work for 4469/4269/4305 + FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); + WaitUS(EM_ZERO_GAP); + TurnReadLFOn(EM_ZERO_GAP); } } } -void EM4xLogin(uint32_t Password) { - - uint8_t fwd_bit_count; +void EM4xLogin(uint32_t pwd) { + uint8_t len; forward_ptr = forwardLink_data; - fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN ); - fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 ); - SendForward(fwd_bit_count); - - //Wait for command to complete + len = Prepare_Cmd( FWD_CMD_LOGIN ); + len += Prepare_Data( pwd & 0xFFFF, pwd >> 16 ); + SendForward(len); WaitMS(20); } -void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) { +void EM4xReadWord(uint8_t addr, uint32_t pwd, uint8_t usepwd) { - uint8_t fwd_bit_count; - uint8_t *dest = BigBuf_get_addr(); - uint16_t bufsize = BigBuf_max_traceLen(); // ICEMAN: this tries to fill up all tracelog space - uint32_t i = 0; + LED_A_ON(); - // Clear destination buffer before sending the command + uint8_t len; + + //clear buffer now so it does not interfere with timing later BigBuf_Clear_ext(false); - //If password mode do login - if (PwdMode == 1) EM4xLogin(Pwd); + if (usepwd) EM4xLogin(pwd); forward_ptr = forwardLink_data; - fwd_bit_count = Prepare_Cmd( FWD_CMD_READ ); - fwd_bit_count += Prepare_Addr( Address ); + len = Prepare_Cmd( FWD_CMD_READ ); + len += Prepare_Addr( addr ); - SendForward(fwd_bit_count); + SendForward(len); - // Now do the acquisition - // ICEMAN, change to the one in lfsampling.c - i = 0; - for(;;) { - if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) { - AT91C_BASE_SSC->SSC_THR = 0x43; - } - if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) { - dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR; - ++i; - if (i >= bufsize) break; - } - } + DoAcquisition_config(TRUE); - FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off + FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); cmd_send(CMD_ACK,0,0,0,0,0); - LED_D_OFF(); + LED_A_OFF(); } -void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) { +void EM4xWriteWord(uint32_t flag, uint32_t data, uint32_t pwd) { - uint8_t fwd_bit_count; - - //If password mode do login - if (PwdMode == 1) EM4xLogin(Pwd); + LED_A_ON(); + + bool usePwd = (flag & 0xF); + uint8_t addr = (flag >> 8) & 0xFF; + uint8_t len; + + //clear buffer now so it does not interfere with timing later + BigBuf_Clear_ext(false); + + if (usePwd) EM4xLogin(pwd); forward_ptr = forwardLink_data; - fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE ); - fwd_bit_count += Prepare_Addr( Address ); - fwd_bit_count += Prepare_Data( Data&0xFFFF, Data>>16 ); + len = Prepare_Cmd( FWD_CMD_WRITE ); + len += Prepare_Addr( addr ); + len += Prepare_Data( data & 0xFFFF, data >> 16 ); - SendForward(fwd_bit_count); + SendForward(len); - //Wait for write to complete + //Wait 20ms for write to complete WaitMS(20); + FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); + cmd_send(CMD_ACK,0,0,0,0,0); + LED_A_OFF(); +} + +/* +Reading a COTAG. + +COTAG needs the reader to send a startsequence and the card has an extreme slow datarate. +because of this, we can "sample" the data signal but we interpreate it to Manchester direct. + +READER START SEQUENCE: +burst 800 us, gap 2.2 msecs +burst 3.6 msecs gap 2.2 msecs +burst 800 us gap 2.2 msecs +pulse 3.6 msecs + +This triggers a COTAG tag to response +*/ +void Cotag(uint32_t arg0) { +#ifndef OFF +# define OFF { FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); WaitUS(2035); } +#endif +#ifndef ON +# define ON(x) { FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD); WaitUS((x)); } +#endif + uint8_t rawsignal = arg0 & 0xF; + + LED_A_ON(); + + // Switching to LF image on FPGA. This might empty BigBuff + FpgaDownloadAndGo(FPGA_BITSTREAM_LF); + + //clear buffer now so it does not interfere with timing later + BigBuf_Clear_ext(false); + + // Set up FPGA, 132kHz to power up the tag + FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 89); + FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD); + + // Connect the A/D to the peak-detected low-frequency path. + SetAdcMuxFor(GPIO_MUXSEL_LOPKD); + + // Now set up the SSC to get the ADC samples that are now streaming at us. + FpgaSetupSsc(); + + // start clock - 1.5ticks is 1us + StartTicks(); + + //send COTAG start pulse + ON(740) OFF + ON(3330) OFF + ON(740) OFF + ON(1000) + + switch(rawsignal) { + case 0: doCotagAcquisition(50000); break; + case 1: doCotagAcquisitionManchester(); break; + case 2: DoAcquisition_config(TRUE); break; + } + + // Turn the field off FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off - LED_D_OFF(); + cmd_send(CMD_ACK,0,0,0,0,0); + LED_A_OFF(); } + +/* +* EM4305 support +*/