X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/proxmark3-svn/blobdiff_plain/715d74c5be4215d57f3d9d6e874018a959d022c9..bb42a03ef1318442fa0e8e2e07c7dbf8bd49fc96:/tools/at91sam7s256-wiggler.cfg?ds=sidebyside

diff --git a/tools/at91sam7s256-wiggler.cfg b/tools/at91sam7s256-wiggler.cfg
index 83156fe5..83180dc9 100644
--- a/tools/at91sam7s256-wiggler.cfg
+++ b/tools/at91sam7s256-wiggler.cfg
@@ -1,39 +1,39 @@
-telnet_port 4444
-gdb_port 3333
-
-interface parport
-parport_port 0x378
-parport_cable wiggler
-jtag_speed 0
-jtag_nsrst_delay 200
-jtag_ntrst_delay 200
-
-reset_config srst_only srst_pulls_trst
-
-jtag newtap sam7x256 cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0x3f0f0f0f
-#jtag newtap xilinx tap -irlen 6 -ircapture 0x1 -irmask 0xf -expected-id 0x1c1a093
-
-target create sam7x256.cpu arm7tdmi -endian little -chain-position sam7x256.cpu -variant arm7tdmi
-sam7x256.cpu configure -event reset-init {
-	# disable watchdog
-	mww 0xfffffd44 0x00008000
-	# enable user reset
-	mww 0xfffffd08 0xa5000001
-	# CKGR_MOR : enable the main oscillator
-	mww 0xfffffc20 0x00000601
-	sleep 10
-	# CKGR_PLLR:  16 MHz * (5+1) /1 = 96Mhz
-	mww 0xfffffc2c 0x00051c01
-	sleep 10
-	# PMC_MCKR : MCK = PLL / 2 = 48 MHz
-	mww 0xfffffc30 0x00000007
-	sleep 10
-	# MC_FMR: flash mode (FWS=1,FMCN=60)
-	mww 0xffffff60 0x003c0100
-	sleep 100
-}
-
-gdb_memory_map enable
-
-sam7x256.cpu configure -work-area-virt 0 -work-area-phys 0x00200000 -work-area-size 0x10000 -work-area-backup 0
-flash bank at91sam7 0 0 0 0 0
+telnet_port 4444
+gdb_port 3333
+
+interface parport
+parport_port 0x378
+parport_cable wiggler
+jtag_speed 0
+jtag_nsrst_delay 200
+jtag_ntrst_delay 200
+
+reset_config srst_only srst_pulls_trst
+
+jtag newtap sam7x256 cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0x3f0f0f0f
+#jtag newtap xilinx tap -irlen 6 -ircapture 0x1 -irmask 0xf -expected-id 0x1c1a093
+
+target create sam7x256.cpu arm7tdmi -endian little -chain-position sam7x256.cpu -variant arm7tdmi
+sam7x256.cpu configure -event reset-init {
+	# disable watchdog
+	mww 0xfffffd44 0x00008000
+	# enable user reset
+	mww 0xfffffd08 0xa5000001
+	# CKGR_MOR : enable the main oscillator
+	mww 0xfffffc20 0x00000601
+	sleep 10
+	# CKGR_PLLR:  16 MHz * (5+1) /1 = 96Mhz
+	mww 0xfffffc2c 0x00051c01
+	sleep 10
+	# PMC_MCKR : MCK = PLL / 2 = 48 MHz
+	mww 0xfffffc30 0x00000007
+	sleep 10
+	# MC_FMR: flash mode (FWS=1,FMCN=60)
+	mww 0xffffff60 0x003c0100
+	sleep 100
+}
+
+gdb_memory_map enable
+
+sam7x256.cpu configure -work-area-virt 0 -work-area-phys 0x00200000 -work-area-size 0x10000 -work-area-backup 0
+flash bank at91sam7 0 0 0 0 0