X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/proxmark3-svn/blobdiff_plain/76471e5d1734786f6095c0b689fa49c5f6e92136..539fd59ebe7f3ed79a7d9327d4499aa42fd47382:/armsrc/lfops.c diff --git a/armsrc/lfops.c b/armsrc/lfops.c index 9290007c..c80700ae 100644 --- a/armsrc/lfops.c +++ b/armsrc/lfops.c @@ -60,19 +60,19 @@ void ModThenAcquireRawAdcSamples125k(uint32_t delay_off, uint32_t periods, uint3 while(*command != '\0' && *command != ' ') { FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); LED_D_OFF(); - SpinDelayUs(delay_off); + WaitUS(delay_off); FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor); FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD); LED_D_ON(); if(*(command++) == '0') - SpinDelayUs(period_0); // ICEMAN: problem with (us) clock is 21.3us increments + WaitUS(period_0); else - SpinDelayUs(period_1); // ICEMAN: problem with (us) clock is 21.3us increments + WaitUS(period_1); } FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); LED_D_OFF(); - SpinDelayUs(delay_off); // ICEMAN: problem with (us) clock is 21.3us increments + WaitUS(delay_off); FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor); FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD); @@ -225,20 +225,20 @@ void WriteTIbyte(uint8_t b) // modulate 8 bits out to the antenna for (i=0; i<8; i++) { - if (b&(1<> 10); - // where to save it - - SpinDelayCountUs(delay); // ICEMAN: problem with (us) clock is 21.3us increments + + // Give it a bit of time for the resonant antenna to settle. + WaitUS(delay); } // Write one bit to card @@ -1154,7 +1156,7 @@ void T55xxWriteBit(int bit) { else TurnReadLFOn(WRITE_1); FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); - SpinDelayCountUs(WRITE_GAP); // ICEMAN: problem with (us) clock is 21.3us increments + WaitUS(WRITE_GAP); } // Send T5577 reset command then read stream (see if we can identify the start of the stream) @@ -1168,7 +1170,7 @@ void T55xxResetRead(void) { // Trigger T55x7 in mode. FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); - SpinDelayCountUs(START_GAP); // ICEMAN: problem with (us) clock is 21.3us increments + WaitUS(START_GAP); // reset tag - op code 00 T55xxWriteBit(0); @@ -1198,7 +1200,7 @@ void T55xxWriteBlockExt(uint32_t Data, uint8_t Block, uint32_t Pwd, uint8_t arg) // Trigger T55x7 in mode. FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); - SpinDelayCountUs(START_GAP); // ICEMAN: problem with (us) clock is 21.3us increments + WaitUS(START_GAP); // Opcode 10 T55xxWriteBit(1); @@ -1222,10 +1224,11 @@ void T55xxWriteBlockExt(uint32_t Data, uint8_t Block, uint32_t Pwd, uint8_t arg) // Perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550, // so wait a little more) TurnReadLFOn(20 * 1000); - //could attempt to do a read to confirm write took - // as the tag should repeat back the new block - // until it is reset, but to confirm it we would - // need to know the current block 0 config mode + + //could attempt to do a read to confirm write took + // as the tag should repeat back the new block + // until it is reset, but to confirm it we would + // need to know the current block 0 config mode // turn field off FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); @@ -1258,7 +1261,7 @@ void T55xxReadBlock(uint16_t arg0, uint8_t Block, uint32_t Pwd) { // Trigger T55x7 Direct Access Mode with start gap FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); - SpinDelayCountUs(START_GAP); // ICEMAN: problem with (us) clock is 21.3us increments + WaitUS(START_GAP); // Opcode 1[page] T55xxWriteBit(1); @@ -1298,7 +1301,7 @@ void T55xxWakeUp(uint32_t Pwd){ // Trigger T55x7 Direct Access Mode FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); - SpinDelayCountUs(START_GAP); // ICEMAN: problem with (us) clock is 21.3us increments + WaitUS(START_GAP); // Opcode 10 T55xxWriteBit(1); @@ -1514,9 +1517,9 @@ void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo) { //----------------------------------- // EM4469 / EM4305 routines //----------------------------------- -#define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored -#define FWD_CMD_WRITE 0xA -#define FWD_CMD_READ 0x9 +#define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored +#define FWD_CMD_WRITE 0xA +#define FWD_CMD_READ 0x9 #define FWD_CMD_DISABLE 0x5 uint8_t forwardLink_data[64]; //array of forwarded bits @@ -1535,7 +1538,7 @@ uint8_t * fwd_write_ptr; //forwardlink bit pointer // WRITE_1 = 256 32*8; (32*8) // These timings work for 4469/4269/4305 (with the 55*8 above) -// WRITE_0 = 23*8 , 9*8 SpinDelayUs(23*8); +// WRITE_0 = 23*8 , 9*8 uint8_t Prepare_Cmd( uint8_t cmd ) { @@ -1629,20 +1632,20 @@ void SendForward(uint8_t fwd_bit_count) { fwd_bit_sz--; //prepare next bit modulation fwd_write_ptr++; FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off - SpinDelayUs(55*8); //55 cycles off (8us each)for 4305 // ICEMAN: problem with (us) clock is 21.3us increments + WaitUS(55*8); //55 cycles off (8us each)for 4305 // ICEMAN: problem with (us) clock is 21.3us increments FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on - SpinDelayUs(16*8); //16 cycles on (8us each) // ICEMAN: problem with (us) clock is 21.3us increments + WaitUS(16*8); //16 cycles on (8us each) // ICEMAN: problem with (us) clock is 21.3us increments // now start writting while(fwd_bit_sz-- > 0) { //prepare next bit modulation if(((*fwd_write_ptr++) & 1) == 1) - SpinDelayUs(32*8); //32 cycles at 125Khz (8us each) // ICEMAN: problem with (us) clock is 21.3us increments + WaitUS(32*8); //32 cycles at 125Khz (8us each) // ICEMAN: problem with (us) clock is 21.3us increments else { //These timings work for 4469/4269/4305 (with the 55*8 above) FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off - SpinDelayUs(23*8); //16-4 cycles off (8us each) // ICEMAN: problem with (us) clock is 21.3us increments + WaitUS(16*8); //16-4 cycles off (8us each) // ICEMAN: problem with (us) clock is 21.3us increments FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on - SpinDelayUs(9*8); //16 cycles on (8us each) // ICEMAN: problem with (us) clock is 21.3us increments + WaitUS(16*8); //16 cycles on (8us each) // ICEMAN: problem with (us) clock is 21.3us increments } } } @@ -1650,22 +1653,20 @@ void SendForward(uint8_t fwd_bit_count) { void EM4xLogin(uint32_t Password) { uint8_t fwd_bit_count; - forward_ptr = forwardLink_data; fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN ); fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 ); - SendForward(fwd_bit_count); //Wait for command to complete - SpinDelay(20); + WaitMS(20); } void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) { uint8_t fwd_bit_count; uint8_t *dest = BigBuf_get_addr(); - uint16_t bufsize = BigBuf_max_traceLen(); + uint16_t bufsize = BigBuf_max_traceLen(); // ICEMAN: this tries to fill up all tracelog space uint32_t i = 0; // Clear destination buffer before sending the command @@ -1678,14 +1679,10 @@ void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) { fwd_bit_count = Prepare_Cmd( FWD_CMD_READ ); fwd_bit_count += Prepare_Addr( Address ); - // Connect the A/D to the peak-detected low-frequency path. - SetAdcMuxFor(GPIO_MUXSEL_LOPKD); - // Now set up the SSC to get the ADC samples that are now streaming at us. - FpgaSetupSsc(); - SendForward(fwd_bit_count); // Now do the acquisition + // ICEMAN, change to the one in lfsampling.c i = 0; for(;;) { if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) { @@ -1718,7 +1715,7 @@ void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode SendForward(fwd_bit_count); //Wait for write to complete - SpinDelay(20); + WaitMS(20); FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off LED_D_OFF(); }