X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/proxmark3-svn/blobdiff_plain/7cc204bff881ce1d1833d8e93469f6bbba80c70e..c936a22f1921f5dd8ebf49a8d1a0fab60337dd31:/armsrc/lfops.c

diff --git a/armsrc/lfops.c b/armsrc/lfops.c
index a0fa870b..9b9caaf0 100644
--- a/armsrc/lfops.c
+++ b/armsrc/lfops.c
@@ -15,7 +15,7 @@
 #include "crc16.h"
 #include "string.h"
 
-void AcquireRawAdcSamples125k(int divisor)
+void LFSetupFPGAForADC(int divisor, bool lf_field)
 {
 	FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
 	if ( (divisor == 1) || (divisor < 0) || (divisor > 255) )
@@ -25,23 +25,30 @@ void AcquireRawAdcSamples125k(int divisor)
 	else
 		FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor);
 
-	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | (lf_field ? FPGA_LF_ADC_READER_FIELD : 0));
 
 	// Connect the A/D to the peak-detected low-frequency path.
 	SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
-
 	// Give it a bit of time for the resonant antenna to settle.
 	SpinDelay(50);
-
 	// Now set up the SSC to get the ADC samples that are now streaming at us.
 	FpgaSetupSsc();
+}
+
+void AcquireRawAdcSamples125k(int divisor)
+{
+	LFSetupFPGAForADC(divisor, true);
+	DoAcquisition125k(-1);
+}
 
-	// Now call the acquisition routine
-	DoAcquisition125k();
+void SnoopLFRawAdcSamples(int divisor, int trigger_threshold)
+{
+	LFSetupFPGAForADC(divisor, false);
+	DoAcquisition125k(trigger_threshold);
 }
 
 // split into two routines so we can avoid timing issues after sending commands //
-void DoAcquisition125k(void)
+void DoAcquisition125k(int trigger_threshold)
 {
 	uint8_t *dest = (uint8_t *)BigBuf;
 	int n = sizeof(BigBuf);
@@ -56,9 +63,12 @@ void DoAcquisition125k(void)
 		}
 		if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
 			dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
-			i++;
 			LED_D_OFF();
-			if (i >= n) break;
+			if (trigger_threshold != -1 && dest[i] < trigger_threshold)
+				continue;
+			else
+				trigger_threshold = -1;
+			if (++i >= n) break;
 		}
 	}
 	Dbprintf("buffer samples: %02x %02x %02x %02x %02x %02x %02x %02x ...",
@@ -85,7 +95,7 @@ void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1,
 	else
 		FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
 
-	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
 
 	// Give it a bit of time for the resonant antenna to settle.
 	SpinDelay(50);
@@ -105,7 +115,7 @@ void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1,
 		else
 			FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
 
-		FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+		FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
 		LED_D_ON();
 		if(*(command++) == '0')
 			SpinDelayUs(period_0);
@@ -120,10 +130,10 @@ void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1,
 	else
 		FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
 
-	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
 
 	// now do the read
-	DoAcquisition125k();
+	DoAcquisition125k(-1);
 }
 
 /* blank r/w tag data stream
@@ -609,7 +619,7 @@ void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
 
 	FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
 	FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
-	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
 
 	// Connect the A/D to the peak-detected low-frequency path.
 	SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
@@ -823,7 +833,7 @@ void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
 
 	FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
 	FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
-	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
 
 	// Connect the A/D to the peak-detected low-frequency path.
 	SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
@@ -917,98 +927,24 @@ void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
 				} else {
 					n=(n+1)/6;			// fc/10 in sets of 6
 				}
-				switch (n) {			// stuff appropriate bits in buffer
-					case 0:
-					case 1:	// one bit
-						dest[i++]=dest[idx-1]^1;
-						//Dbprintf("%d",dest[idx-1]);
-						break;
-					case 2: // two bits
-						dest[i++]=dest[idx-1]^1;
-						dest[i++]=dest[idx-1]^1;
-						//Dbprintf("%d",dest[idx-1]);
-						//Dbprintf("%d",dest[idx-1]);
-						break;
-					case 3: // 3 bit start of frame markers
-						for(int j=0; j<3; j++){
-						  dest[i++]=dest[idx-1]^1;
-						//  Dbprintf("%d",dest[idx-1]);
-						}
-						break;
-					case 4:
-						for(int j=0; j<4; j++){
-						  dest[i++]=dest[idx-1]^1;
-						//  Dbprintf("%d",dest[idx-1]);
-						}
-						break;
-					case 5:
-						for(int j=0; j<5; j++){
-						  dest[i++]=dest[idx-1]^1;
-						//  Dbprintf("%d",dest[idx-1]);
-						}
-						break;
-					case 6:
-						for(int j=0; j<6; j++){
-						  dest[i++]=dest[idx-1]^1;
-						//  Dbprintf("%d",dest[idx-1]);
-						}
-						break;
-					case 7:
-						for(int j=0; j<7; j++){
-						  dest[i++]=dest[idx-1]^1;
-						//  Dbprintf("%d",dest[idx-1]);
-						}
-						break;
-					case 8:
-						for(int j=0; j<8; j++){
-						  dest[i++]=dest[idx-1]^1;
-						//  Dbprintf("%d",dest[idx-1]);
-						}
-						break;
-					case 9:
-						for(int j=0; j<9; j++){
-						  dest[i++]=dest[idx-1]^1;
-						//  Dbprintf("%d",dest[idx-1]);
-						}
-						break;
-					case 10:
-						for(int j=0; j<10; j++){
-						  dest[i++]=dest[idx-1]^1;
-						//  Dbprintf("%d",dest[idx-1]);
-						}
-						break;
-					case 11:
-						for(int j=0; j<11; j++){
-						  dest[i++]=dest[idx-1]^1;
-						//  Dbprintf("%d",dest[idx-1]);
-						}
-						break;
-					case 12:
-						for(int j=0; j<12; j++){
-						  dest[i++]=dest[idx-1]^1;
-						 // Dbprintf("%d",dest[idx-1]);
-						}
-						break;
-					default:	// this shouldn't happen, don't stuff any bits
-						//Dbprintf("%d",dest[idx-1]);
-						break;
-				}
+				if (n < 13){
+                  for(int j=0; j<n; j++){
+                    dest[i++]=dest[idx-1]^1;
+                  }
+                }
 				n=0;
 				lastval=dest[idx];
 			}
 		}//end for
-		/*for(int j=0; j<64;j+=8){
-		  Dbprintf("%d%d%d%d%d%d%d%d",dest[j],dest[j+1],dest[j+2],dest[j+3],dest[j+4],dest[j+5],dest[j+6],dest[j+7]);
-		}
-		Dbprintf("\n");*/
 		m=i;
 		WDT_HIT();
 		
-        for( idx=0; idx<m-9; idx++) {
-	  if ( !(dest[idx]) && !(dest[idx+1]) && !(dest[idx+2]) && !(dest[idx+3]) && !(dest[idx+4]) && !(dest[idx+5]) && !(dest[idx+6]) && !(dest[idx+7]) && !(dest[idx+8])&& (dest[idx+9])){
-		found=1;
-		//idx+=9;
-		if (found) {
+		uint8_t mask[] = {0,0,0,0,0,0,0,0,0,1};
+		for( idx=0; idx < m - 64; idx++) {
+
+ 	    	if ( memcmp(dest + idx, mask, sizeof(mask)) ) continue;
+ 	    	    found=1;
+                    m=idx;
 		    Dbprintf("%d%d%d%d%d%d%d%d",dest[idx],   dest[idx+1],   dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7]);
 		    Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+8], dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15]);			  
 		    Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+16],dest[idx+17],dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23]);
@@ -1026,7 +962,7 @@ void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
 		       version <<=1;
 		       if (dest[idx+j]) version |= 1;
 		    }
-		    for(int j=19;j<27;j++){
+		    for(int j=18;j<26;j++){
 		       //Dbprintf("%d",dest[idx+j]);
 		       unknown <<=1;
 		       if (dest[idx+j]) unknown |= 1;
@@ -1055,20 +991,15 @@ void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
 			LED_D_OFF();
 		}
 		// if we're only looking for one tag 
-		if (findone){
+		if (found){
 			//*high = hi;
 			//*low = lo;
 			LED_A_OFF();
 			return;
 		}
       
-		//hi=0;
-		//lo=0;
 		found=0;
-	  }
-		
-	}
-	}
+	  }		
 	WDT_HIT();
 }
 
@@ -1141,7 +1072,7 @@ void T55xxWriteBit(int bit)
 {
 	FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
 	FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
-	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
 	if (bit == 0)
 		SpinDelayUs(WRITE_0);
 	else
@@ -1157,7 +1088,7 @@ void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMod
 
 	FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
 	FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
-	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
 
 	// Give it a bit of time for the resonant antenna to settle.
 	// And for the tag to fully power up
@@ -1189,7 +1120,7 @@ void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMod
 	// Now perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
 	// so wait a little more)
 	FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
-	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
 	SpinDelay(20);
 	FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
 }
@@ -1211,7 +1142,7 @@ void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
   
 	LED_D_ON();
 	FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
-	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
   
 	// Give it a bit of time for the resonant antenna to settle.
 	// And for the tag to fully power up
@@ -1237,7 +1168,7 @@ void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
   
   // Turn field on to read the response
 	FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
-	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
   
 	// Now do the acquisition
 	i = 0;
@@ -1276,7 +1207,7 @@ void T55xxReadTrace(void){
   
 	LED_D_ON();
 	FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
-	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
   
 	// Give it a bit of time for the resonant antenna to settle.
 	// And for the tag to fully power up
@@ -1292,7 +1223,7 @@ void T55xxReadTrace(void){
   
   // Turn field on to read the response
 	FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
-	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
   
 	// Now do the acquisition
 	i = 0;
@@ -1983,7 +1914,7 @@ void SendForward(uint8_t fwd_bit_count) {
   //Field on
   FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
   FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
-  FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+  FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
   
   // Give it a bit of time for the resonant antenna to settle.
   // And for the tag to fully power up
@@ -1995,7 +1926,7 @@ void SendForward(uint8_t fwd_bit_count) {
   FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
   SpinDelayUs(55*8); //55 cycles off (8us each)for 4305
   FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
-  FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);//field on
+  FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
   SpinDelayUs(16*8); //16 cycles on (8us each)
   
   // now start writting
@@ -2007,7 +1938,7 @@ void SendForward(uint8_t fwd_bit_count) {
       FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
       SpinDelayUs(23*8); //16-4 cycles off (8us each)
       FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
-      FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);//field on
+      FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
       SpinDelayUs(9*8); //16 cycles on (8us each)
     }
   }