X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/proxmark3-svn/blobdiff_plain/802a36162a7a5452ad1b276399087df11b46ccd1..58a0fa747eab16c1997da619c2994a9cda640b00:/fpga/lo_simulate.v

diff --git a/fpga/lo_simulate.v b/fpga/lo_simulate.v
index 9e3cd50a..57e602a2 100644
--- a/fpga/lo_simulate.v
+++ b/fpga/lo_simulate.v
@@ -1,56 +1,56 @@
-//-----------------------------------------------------------------------------
-// The way that we connect things in low-frequency simulation mode. In this
-// case just pass everything through to the ARM, which can bit-bang this
-// (because it is so slow).
-//
-// Jonathan Westhues, April 2006
-//-----------------------------------------------------------------------------
-
-module lo_simulate(
-    pck0, ck_1356meg, ck_1356megb,
-    pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
-    adc_d, adc_clk,
-    ssp_frame, ssp_din, ssp_dout, ssp_clk,
-    cross_hi, cross_lo,
+//-----------------------------------------------------------------------------
+// The way that we connect things in low-frequency simulation mode. In this
+// case just pass everything through to the ARM, which can bit-bang this
+// (because it is so slow).
+//
+// Jonathan Westhues, April 2006
+//-----------------------------------------------------------------------------
+
+module lo_simulate(
+    pck0, ck_1356meg, ck_1356megb,
+    pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
+    adc_d, adc_clk,
+    ssp_frame, ssp_din, ssp_dout, ssp_clk,
+    cross_hi, cross_lo,
     dbg,
-	 divisor
-);
-    input pck0, ck_1356meg, ck_1356megb;
-    output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
-    input [7:0] adc_d;
-    output adc_clk;
-    input ssp_dout;
-    output ssp_frame, ssp_din, ssp_clk;
-    input cross_hi, cross_lo;
+	 divisor
+);
+    input pck0, ck_1356meg, ck_1356megb;
+    output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
+    input [7:0] adc_d;
+    output adc_clk;
+    input ssp_dout;
+    output ssp_frame, ssp_din, ssp_clk;
+    input cross_hi, cross_lo;
     output dbg;
-	 input [7:0] divisor;
-
-// No logic, straight through.
-assign pwr_oe3 = 1'b0;
-assign pwr_oe1 = ssp_dout;
-assign pwr_oe2 = ssp_dout;
-assign pwr_oe4 = ssp_dout;
-assign ssp_clk = cross_lo;
-assign pwr_lo = 1'b0;
-assign pwr_hi = 1'b0;
-assign dbg = ssp_frame;
+	 input [7:0] divisor;
+
+// No logic, straight through.
+assign pwr_oe3 = 1'b0;
+assign pwr_oe1 = ssp_dout;
+assign pwr_oe2 = ssp_dout;
+assign pwr_oe4 = ssp_dout;
+assign ssp_clk = cross_lo;
+assign pwr_lo = 1'b0;
+assign pwr_hi = 1'b0;
+assign dbg = ssp_frame;
 
 // Divide the clock to be used for the ADC
 reg [7:0] pck_divider;
 reg clk_state;
-
-always @(posedge pck0)
-begin
-	if(pck_divider == divisor[7:0])
-		begin
+
+always @(posedge pck0)
+begin
+	if(pck_divider == divisor[7:0])
+		begin
 			pck_divider <= 8'd0;
-			clk_state = !clk_state;
-		end
-	else
-	begin
-		pck_divider <= pck_divider + 1;
-	end
-end
+			clk_state = !clk_state;
+		end
+	else
+	begin
+		pck_divider <= pck_divider + 1;
+	end
+end
 
 assign adc_clk = ~clk_state;
 
@@ -61,8 +61,8 @@ reg is_high;
 reg is_low;
 reg output_state;
 
-always @(posedge pck0)
-begin
+always @(posedge pck0)
+begin
 	if((pck_divider == 8'd7) && !clk_state) begin
 		is_high = (adc_d >= 8'd200);
 		is_low = (adc_d <= 8'd64);
@@ -78,5 +78,6 @@ begin
 end
 
 assign ssp_frame = output_state;
-
-endmodule
+
+endmodule
+