X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/proxmark3-svn/blobdiff_plain/810f53792ea438c1b70eaa1f934db1e5c96220cb..68410a4892c9679abc0e2cf3c9c1efb95651fa4f:/armsrc/iclass.c?ds=inline

diff --git a/armsrc/iclass.c b/armsrc/iclass.c
index 101ca060..8c3be1f6 100644
--- a/armsrc/iclass.c
+++ b/armsrc/iclass.c
@@ -919,7 +919,7 @@ static void CodeIClassTagAnswer(const uint8_t *cmd, int len)
 	 * The mode FPGA_HF_SIMULATOR_MODULATE_424K_8BIT which we use to simulate tag,
 	 * works like this.
 	 * - A 1-bit input to the FPGA becomes 8 pulses on 423.5kHz (fc/32) (18.88us).
-	 * - A 0-bit inptu to the FPGA becomes an unmodulated time of 18.88us
+	 * - A 0-bit input to the FPGA becomes an unmodulated time of 18.88us
 	 *
 	 * In this mode the SOF can be written as 00011101 = 0x1D
 	 * The EOF can be written as 10111000 = 0xb8
@@ -1296,7 +1296,8 @@ int doIClassSimulation( int simulationMode, uint8_t *reader_mac_buf)
 			receivedCmd[3], receivedCmd[4], receivedCmd[5],
 			receivedCmd[6], receivedCmd[7], receivedCmd[8]);
 			// Do not respond
-			modulated_response = resp_sof; modulated_response_size = 0; //order = 0;
+			modulated_response = resp_sof;
+			modulated_response_size = 0; //order = 0;
 			trace_data = NULL;
 			trace_data_size = 0;
 		}
@@ -1383,63 +1384,62 @@ static int SendIClassAnswer(uint8_t *resp, int respLen, int delay)
 //-----------------------------------------------------------------------------
 static void TransmitIClassCommand(const uint8_t *cmd, int len, int *samples, int *wait)
 {
-  int c;
-  FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD);
-  AT91C_BASE_SSC->SSC_THR = 0x00;
-  FpgaSetupSsc();
-
-   if (wait)
-   {
-     if(*wait < 10) *wait = 10;
-     
-  for(c = 0; c < *wait;) {
-    if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
-      AT91C_BASE_SSC->SSC_THR = 0x00;		// For exact timing!
-      c++;
-    }
-    if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
-      volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;
-      (void)r;
-    }
-    WDT_HIT();
-  }
+	int c;
+	volatile uint32_t r;
+	FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD);
+	AT91C_BASE_SSC->SSC_THR = 0x00;
+	FpgaSetupSsc();
 
-   }
+	if (wait) {
+		if(*wait < 10) *wait = 10;
 
+		for(c = 0; c < *wait;) {
+			if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
+				AT91C_BASE_SSC->SSC_THR = 0x00;		// For exact timing!
+				c++;
+			}
+			if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
+				r = AT91C_BASE_SSC->SSC_RHR;
+				(void)r;
+			}
+			WDT_HIT();
+		}
+	}
 
-  uint8_t sendbyte;
-  bool firstpart = TRUE;
-  c = 0;
-  for(;;) {
-    if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
 
-      // DOUBLE THE SAMPLES!
-      if(firstpart) {
-	sendbyte = (cmd[c] & 0xf0) | (cmd[c] >> 4); 
-      }
-      else {
-	sendbyte = (cmd[c] & 0x0f) | (cmd[c] << 4);
-        c++;
-      }
-      if(sendbyte == 0xff) {
-	sendbyte = 0xfe;
-      }
-      AT91C_BASE_SSC->SSC_THR = sendbyte;
-      firstpart = !firstpart;
+	uint8_t sendbyte;
+	bool firstpart = TRUE;
+	c = 0;
+	for(;;) {
+		if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
 
-      if(c >= len) {
-        break;
-      }
-    }
-    if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
-      volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;
-      (void)r;
-    }
-    WDT_HIT();
-  }
-  if (samples) *samples = (c + *wait) << 3;
-}
+			// DOUBLE THE SAMPLES!
+			if(firstpart) {
+				sendbyte = (cmd[c] & 0xf0) | (cmd[c] >> 4); 
+			}
+			else {
+				sendbyte = (cmd[c] & 0x0f) | (cmd[c] << 4);
+				c++;
+			}
+
+			if(sendbyte == 0xff)
+				sendbyte = 0xfe;
+
+			AT91C_BASE_SSC->SSC_THR = sendbyte;
+			firstpart = !firstpart;
 
+			if(c >= len) break;
+
+		}
+		if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
+			r = AT91C_BASE_SSC->SSC_RHR;
+			(void)r;
+		}
+		
+		WDT_HIT();
+	}
+	if (samples && wait) *samples = (c + *wait) << 3;
+}
 
 //-----------------------------------------------------------------------------
 // Prepare iClass reader command to send to FPGA