X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/proxmark3-svn/blobdiff_plain/8652988d62b19631e498b62a3800f0decb5e743a..987dfb66e2982d229f0681f991b04e325613fc5f:/bootrom/ldscript-flash?ds=inline diff --git a/bootrom/ldscript-flash b/bootrom/ldscript-flash index fa6fb26e..f1bab149 100644 --- a/bootrom/ldscript-flash +++ b/bootrom/ldscript-flash @@ -1,43 +1,63 @@ -MEMORY -{ - /* AT91SAM7S256 has 256k Flash and 64k RAM */ - /* Important note: the correct ORIGIN for bootphase1 is 0x00100000 and for bootphase2 is 0x00100200 - However, this will confuse the currently deployed flash code which expects logical and and not - physical addresses and performs no sanity checks at all. If confronted with physical addresses, - it will happily erase everything and brick the device. So for the time being pretend these addresses - to start at 0x0 while updating all the flash code with proper sanity checks, then come back later and - fix the addresses. -- Henryk Plötz 2009-08-27 */ - bootphase1 : ORIGIN = 0x00000000, LENGTH = 0x200 /* Phase 1 bootloader: Copies real bootloader to RAM */ - bootphase2 : ORIGIN = 0x00000200, LENGTH = 0x2000 - 0x200 /* Main bootloader code, stored in Flash, executed from RAM */ - ram : ORIGIN = 0x00200000, LENGTH = 32K -} - - -SECTIONS -{ - . = 0; - - bootphase1 : { - *(.startup) - *(.bootphase1) - } >bootphase1 - - bootphase2 : { - __bootphase2_start__ = .; - *(.startphase2) - *(.text) - *(.glue_7) - *(.rodata) - *(.data) - . = ALIGN( 32 / 8 ); - __bootphase2_end__ = .; - } >ram AT>bootphase2 - - .bss : { - __bss_start__ = .; - *(.bss) - } >ram - - . = ALIGN( 32 / 8 ); - __bss_end__ = .; -} +/* +----------------------------------------------------------------------------- + This code is licensed to you under the terms of the GNU GPL, version 2 or, + at your option, any later version. See the LICENSE.txt file for the text of + the license. +----------------------------------------------------------------------------- + Bootrom linker script +----------------------------------------------------------------------------- +*/ + +INCLUDE ../common/ldscript.common + +PHDRS +{ + phase1 PT_LOAD; + phase2 PT_LOAD; + bss PT_LOAD; +} + +ENTRY(flashstart) +SECTIONS +{ + .bootphase1 : { + *(.startup) + + . = ALIGN(4); + _version_information_start = .; + KEEP(*(.version_information)); + + . = LENGTH(bootphase1) - 0x4; + LONG(_version_information_start); + } >bootphase1 :phase1 + + .bootphase2 : { + *(.startphase2) + *(.text) + *(.text.*) + *(.eh_frame) + *(.glue_7) + *(.glue_7t) + *(.rodata) + *(.rodata.*) + *(.data) + *(.data.*) + . = ALIGN(4); + } >ram AT>bootphase2 :phase2 + + __bootphase2_src_start__ = LOADADDR(.bootphase2); + __bootphase2_start__ = ADDR(.bootphase2); + __bootphase2_end__ = __bootphase2_start__ + SIZEOF(.bootphase2); + + .bss : { + __bss_start__ = .; + *(.bss) + *(.bss.*) + . = ALIGN(4); + __bss_end__ = .; + } >ram AT>ram :bss + + .commonarea (NOLOAD) : { + *(.commonarea) + } >commonarea +}