X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/proxmark3-svn/blobdiff_plain/8f51ddb0bd8fb7536a07966433061f03d45f65e0..3179383f8549b98eaa977c03105cdec7af5007dc:/armsrc/util.c

diff --git a/armsrc/util.c b/armsrc/util.c
index 00dbdbb8..5b68f513 100644
--- a/armsrc/util.c
+++ b/armsrc/util.c
@@ -11,6 +11,20 @@
 #include "proxmark3.h"
 #include "util.h"
 #include "string.h"
+#include "apps.h"
+
+size_t nbytes(size_t nbits) {
+	return (nbits/8)+((nbits%8)>0);
+}
+
+uint32_t SwapBits(uint32_t value, int nrbits) {
+	int i;
+	uint32_t newvalue = 0;
+	for(i = 0; i < nrbits; i++) {
+		newvalue ^= ((value >> i) & 1) << (nrbits - 1 - i);
+	}
+	return newvalue;
+}
 
 void num_to_bytes(uint64_t n, size_t len, uint8_t* dest)
 {
@@ -211,29 +225,29 @@ void FormatVersionInformation(char *dst, int len, const char *prefix, void *vers
 {
 	struct version_information *v = (struct version_information*)version_information;
 	dst[0] = 0;
-	strncat(dst, prefix, len);
+	strncat(dst, prefix, len-1);
 	if(v->magic != VERSION_INFORMATION_MAGIC) {
-		strncat(dst, "Missing/Invalid version information", len);
+		strncat(dst, "Missing/Invalid version information", len - strlen(dst) - 1);
 		return;
 	}
 	if(v->versionversion != 1) {
-		strncat(dst, "Version information not understood", len);
+		strncat(dst, "Version information not understood", len - strlen(dst) - 1);
 		return;
 	}
 	if(!v->present) {
-		strncat(dst, "Version information not available", len);
+		strncat(dst, "Version information not available", len - strlen(dst) - 1);
 		return;
 	}
 
-	strncat(dst, v->svnversion, len);
+	strncat(dst, v->gitversion, len - strlen(dst) - 1);
 	if(v->clean == 0) {
-		strncat(dst, "-unclean", len);
+		strncat(dst, "-unclean", len - strlen(dst) - 1);
 	} else if(v->clean == 2) {
-		strncat(dst, "-suspect", len);
+		strncat(dst, "-suspect", len - strlen(dst) - 1);
 	}
 
-	strncat(dst, " ", len);
-	strncat(dst, v->buildtime, len);
+	strncat(dst, " ", len - strlen(dst) - 1);
+	strncat(dst, v->buildtime, len - strlen(dst) - 1);
 }
 
 //  -------------------------------------------------------------------------
@@ -281,11 +295,11 @@ void StartCountUS()
 	
 	AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS; // timer disable  
 	AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_XC1; // from timer 0
-
+	
 	AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN;
 	AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN;
 	AT91C_BASE_TCB->TCB_BCR = 1;
-}
+	}
 
 uint32_t RAMFUNC GetCountUS(){
 	return (AT91C_BASE_TC1->TC_CV * 0x8000) + ((AT91C_BASE_TC0->TC_CV / 15) * 10);
@@ -301,3 +315,77 @@ uint32_t RAMFUNC GetDeltaCountUS(){
 }
 
 
+//  -------------------------------------------------------------------------
+//  Timer for iso14443 commands. Uses ssp_clk from FPGA 
+//  -------------------------------------------------------------------------
+void StartCountSspClk()
+{
+	AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC0) | (1 << AT91C_ID_TC1) | (1 << AT91C_ID_TC2);  // Enable Clock to all timers
+	AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_TIOA1 		// XC0 Clock = TIOA1
+							| AT91C_TCB_TC1XC1S_NONE 		// XC1 Clock = none
+							| AT91C_TCB_TC2XC2S_TIOA0;		// XC2 Clock = TIOA0
+
+	// configure TC1 to create a short pulse on TIOA1 when a rising edge on TIOB1 (= ssp_clk from FPGA) occurs:
+	AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS; 				// disable TC1
+	AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK // TC1 Clock = MCK(48MHz)/2 = 24MHz
+							| AT91C_TC_CPCSTOP				// Stop clock on RC compare
+							| AT91C_TC_EEVTEDG_RISING		// Trigger on rising edge of Event
+							| AT91C_TC_EEVT_TIOB			// Event-Source: TIOB1 (= ssp_clk from FPGA = 13,56MHz/16)
+							| AT91C_TC_ENETRG				// Enable external trigger event
+							| AT91C_TC_WAVESEL_UP	 		// Upmode without automatic trigger on RC compare
+							| AT91C_TC_WAVE 				// Waveform Mode
+							| AT91C_TC_AEEVT_SET 			// Set TIOA1 on external event
+							| AT91C_TC_ACPC_CLEAR; 			// Clear TIOA1 on RC Compare
+	AT91C_BASE_TC1->TC_RC = 0x04; 							// RC Compare value = 0x04
+
+	// use TC0 to count TIOA1 pulses
+	AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS;				// disable TC0
+	AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_XC0	 			// TC0 clock = XC0 clock = TIOA1
+							| AT91C_TC_WAVE 				// Waveform Mode
+							| AT91C_TC_WAVESEL_UP	 		// just count
+							| AT91C_TC_ACPA_CLEAR 			// Clear TIOA0 on RA Compare
+							| AT91C_TC_ACPC_SET; 			// Set TIOA0 on RC Compare
+	AT91C_BASE_TC0->TC_RA = 1;								// RA Compare value = 1; pulse width to TC2
+	AT91C_BASE_TC0->TC_RC = 0; 								// RC Compare value = 0; increment TC2 on overflow
+
+	// use TC2 to count TIOA0 pulses (giving us a 32bit counter (TC0/TC2) clocked by ssp_clk)
+	AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKDIS; 				// disable TC2  
+	AT91C_BASE_TC2->TC_CMR = AT91C_TC_CLKS_XC2	 			// TC2 clock = XC2 clock = TIOA0
+							| AT91C_TC_WAVE 				// Waveform Mode
+							| AT91C_TC_WAVESEL_UP;	 		// just count
+	
+	AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN;				// enable TC0
+	AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN;				// enable TC1
+	AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKEN;				// enable TC2
+
+	//
+	// synchronize the counter with the ssp_frame signal. Note: FPGA must be in any iso14446 mode, otherwise the frame signal would not be present 
+	//
+	while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME)); 	// wait for ssp_frame to go high (start of frame)
+	while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME); 		// wait for ssp_frame to be low
+	while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)); 	// wait for ssp_clk to go high
+	// note: up to now two ssp_clk rising edges have passed since the rising edge of ssp_frame
+	// it is now safe to assert a sync signal. This sets all timers to 0 on next active clock edge
+	AT91C_BASE_TCB->TCB_BCR = 1;							// assert Sync (set all timers to 0 on next active clock edge)
+	// at the next (3rd) ssp_clk rising edge, TC1 will be reset (and not generate a clock signal to TC0)
+	// at the next (4th) ssp_clk rising edge, TC0 (the low word of our counter) will be reset. From now on,
+	// whenever the last three bits of our counter go 0, we can be sure to be in the middle of a frame transfer.
+	// (just started with the transfer of the 4th Bit).
+	// The high word of the counter (TC2) will not reset until the low word (TC0) overflows. Therefore need to wait quite some time before
+	// we can use the counter.
+	while (AT91C_BASE_TC0->TC_CV < 0xFFF0);
+}
+
+
+uint32_t RAMFUNC GetCountSspClk(){
+	uint32_t tmp_count;
+	tmp_count = (AT91C_BASE_TC2->TC_CV << 16) | AT91C_BASE_TC0->TC_CV;
+	if ((tmp_count & 0x0000ffff) == 0) { //small chance that we may have missed an increment in TC2
+		return (AT91C_BASE_TC2->TC_CV << 16);
+	} 
+	else {
+		return tmp_count;
+	}
+}
+
+