X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/proxmark3-svn/blobdiff_plain/aaa1a9a2dcb8b9f2b6acd937f84464daa50ecad6..5d15891e2bd429b5f30e57f2ab3a3481358b79d1:/armsrc/util.c

diff --git a/armsrc/util.c b/armsrc/util.c
index 4e74b88d..37fe3f43 100644
--- a/armsrc/util.c
+++ b/armsrc/util.c
@@ -8,30 +8,28 @@
 // Utility functions used in many places, not specific to any piece of code.
 //-----------------------------------------------------------------------------
 
-#include "proxmark3.h"
 #include "util.h"
-#include "string.h"
-#include "apps.h"
-#include "BigBuf.h"
-
-
 
 void print_result(char *name, uint8_t *buf, size_t len) {
-   uint8_t *p = buf;
+	uint8_t *p = buf;
 
-   if ( len % 16 == 0 ) {
-	   for(; p-buf < len; p += 16)
-       Dbprintf("[%s:%d/%d] %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
+	if ( len % 16 == 0 ) {
+		for(; p-buf < len; p += 16)
+			Dbprintf("[%s:%d/%d] %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
 				name,
 				p-buf,
 				len,
 				p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7],p[8], p[9], p[10], p[11], p[12], p[13], p[14], p[15]
-	   );
-   }
-   else {
-   for(; p-buf < len; p += 8)
-       Dbprintf("[%s:%d/%d] %02x %02x %02x %02x %02x %02x %02x %02x", name, p-buf, len, p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]);
-   }
+			);
+	}
+	else {
+		for(; p-buf < len; p += 8)
+			Dbprintf("[%s:%d/%d] %02x %02x %02x %02x %02x %02x %02x %02x",
+				name,
+				p-buf,
+				len,
+				p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]);
+	}
 }
 
 size_t nbytes(size_t nbits) {
@@ -46,19 +44,33 @@ uint32_t SwapBits(uint32_t value, int nrbits) {
 	return newvalue;
 }
 
-void num_to_bytes(uint64_t n, size_t len, uint8_t* dest)
-{
+/*
+ ref  http://www.csm.ornl.gov/~dunigan/crc.html
+ Returns the value v with the bottom b [0,32] bits reflected. 
+ Example: reflect(0x3e23L,3) == 0x3e26
+*/
+uint32_t reflect(uint32_t v, int b) {
+	uint32_t t = v;
+	for ( int i = 0; i < b; ++i) {
+		if (t & 1)
+			v |=  BITMASK((b-1)-i);
+		else
+			v &= ~BITMASK((b-1)-i);
+		t >>= 1;
+	}
+	return v;
+}
+
+void num_to_bytes(uint64_t n, size_t len, uint8_t* dest) {
 	while (len--) {
 		dest[len] = (uint8_t) n;
 		n >>= 8;
 	}
 }
 
-uint64_t bytes_to_num(uint8_t* src, size_t len)
-{
+uint64_t bytes_to_num(uint8_t* src, size_t len) {
 	uint64_t num = 0;
-	while (len--)
-	{
+	while (len--) {
 		num = (num << 8) | (*src);
 		src++;
 	}
@@ -66,7 +78,7 @@ uint64_t bytes_to_num(uint8_t* src, size_t len)
 }
 
 // RotateLeft - Ultralight, Desfire
-void rol(uint8_t *data, const size_t len){
+void rol(uint8_t *data, const size_t len) {
     uint8_t first = data[0];
     for (size_t i = 0; i < len-1; i++) {
         data[i] = data[i+1];
@@ -81,13 +93,11 @@ void lsl (uint8_t *data, size_t len) {
     data[len - 1] <<= 1;
 }
 
-int32_t le24toh (uint8_t data[3])
-{
+int32_t le24toh (uint8_t data[3]) {
     return (data[2] << 16) | (data[1] << 8) | data[0];
 }
 
-void LEDsoff()
-{
+void LEDsoff() {
 	LED_A_OFF();
 	LED_B_OFF();
 	LED_C_OFF();
@@ -95,8 +105,7 @@ void LEDsoff()
 }
 
 // LEDs: R(C) O(A) G(B) -- R(D) [1, 2, 4 and 8]
-void LED(int led, int ms)
-{
+void LED(int led, int ms) {
 	if (led & LED_RED)
 		LED_C_ON();
 	if (led & LED_ORANGE)
@@ -121,13 +130,11 @@ void LED(int led, int ms)
 		LED_D_OFF();
 }
 
-
 // Determine if a button is double clicked, single clicked,
 // not clicked, or held down (for ms || 1sec)
 // In general, don't use this function unless you expect a
 // double click, otherwise it will waste 500ms -- use BUTTON_HELD instead
-int BUTTON_CLICKED(int ms)
-{
+int BUTTON_CLICKED(int ms) {
 	// Up to 500ms in between clicks to mean a double click
 	int ticks = (48000 * (ms ? ms : 1000)) >> 10;
 
@@ -189,8 +196,7 @@ int BUTTON_CLICKED(int ms)
 }
 
 // Determine if a button is held down
-int BUTTON_HELD(int ms)
-{
+int BUTTON_HELD(int ms) {
 	// If button is held for one second
 	int ticks = (48000 * (ms ? ms : 1000)) >> 10;
 
@@ -229,8 +235,7 @@ int BUTTON_HELD(int ms)
 
 // attempt at high resolution microsecond timer
 // beware: timer counts in 21.3uS increments (1024/48Mhz)
-void SpinDelayUs(int us)
-{
+void SpinDelayUs(int us) {
 	int ticks = (48*us) >> 10;
 
 	// Borrow a PWM unit for my real-time clock
@@ -251,8 +256,7 @@ void SpinDelayUs(int us)
 	}
 }
 
-void SpinDelay(int ms)
-{
+void SpinDelay(int ms) {
   // convert to uS and call microsecond delay function
 	SpinDelayUs(ms*1000);
 }
@@ -262,8 +266,7 @@ void SpinDelay(int ms)
  * verifies the magic properties, then stores a formatted string, prefixed by
  * prefix in dst.
  */
-void FormatVersionInformation(char *dst, int len, const char *prefix, void *version_information)
-{
+void FormatVersionInformation(char *dst, int len, const char *prefix, void *version_information) {
 	struct version_information *v = (struct version_information*)version_information;
 	dst[0] = 0;
 	strncat(dst, prefix, len-1);
@@ -302,8 +305,7 @@ void FormatVersionInformation(char *dst, int len, const char *prefix, void *vers
 //	ti = GetTickCount() - ti;
 //	Dbprintf("timer(1s): %d t=%d", ti, GetTickCount());
 
-void StartTickCount()
-{
+void StartTickCount() {
 	// This timer is based on the slow clock. The slow clock frequency is between 22kHz and 40kHz.
 	// We can determine the actual slow clock frequency by looking at the Main Clock Frequency Register.
     uint16_t mainf = AT91C_BASE_PMC->PMC_MCFR & 0xffff;		// = 16 * main clock frequency (16MHz) / slow clock frequency
@@ -322,8 +324,7 @@ uint32_t RAMFUNC GetTickCount(){
 //  -------------------------------------------------------------------------
 //  microseconds timer 
 //  -------------------------------------------------------------------------
-void StartCountUS()
-{
+void StartCountUS() {
 	AT91C_BASE_PMC->PMC_PCER |= (0x1 << 12) | (0x1 << 13) | (0x1 << 14);
 //	AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC1XC1S_TIOA0;
 	AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_TIOA0 | AT91C_TCB_TC2XC2S_NONE;
@@ -339,32 +340,41 @@ void StartCountUS()
 	AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS; // timer disable  
 	AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_XC1; // from timer 0
 	
-	AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN;
-	AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN;
+	AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
+	AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
 	AT91C_BASE_TCB->TCB_BCR = 1;
-	}
+	
+	while (AT91C_BASE_TC1->TC_CV >= 1);
+}
 
 uint32_t RAMFUNC GetCountUS(){
 	//return (AT91C_BASE_TC1->TC_CV * 0x8000) + ((AT91C_BASE_TC0->TC_CV / 15) * 10);
 	//  By suggestion from PwPiwi, http://www.proxmark.org/forum/viewtopic.php?pid=17548#p17548
-	return (AT91C_BASE_TC1->TC_CV * 0x8000) + ((AT91C_BASE_TC0->TC_CV * 2) / 3); 
+	//return (AT91C_BASE_TC1->TC_CV * 0x8000) + ((AT91C_BASE_TC0->TC_CV * 2) / 3); 
+	return (AT91C_BASE_TC1->TC_CV * 0x8000) + ((AT91C_BASE_TC0->TC_CV << 1) / 3); 
+	//return (AT91C_BASE_TC1->TC_CV << 16) | ((AT91C_BASE_TC0->TC_CV << 1) / 3); 
+}
+void ResetUSClock(void) {	
+	//enable clock of timer and software trigger
+	AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
+	AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
+	while (AT91C_BASE_TC1->TC_CV >= 1);
 }
 
-static uint32_t GlobalUsCounter = 0;
+// static uint32_t GlobalUsCounter = 0;
 
-uint32_t RAMFUNC GetDeltaCountUS(){
-	uint32_t g_cnt = GetCountUS();
-	uint32_t g_res = g_cnt - GlobalUsCounter;
-	GlobalUsCounter = g_cnt;
-	return g_res;
-}
+// uint32_t RAMFUNC GetDeltaCountUS(){
+	// uint32_t g_cnt = GetCountUS();
+	// uint32_t g_res = g_cnt - GlobalUsCounter;
+	// GlobalUsCounter = g_cnt;
+	// return g_res;
+// }
 
 
 //  -------------------------------------------------------------------------
 //  Timer for iso14443 commands. Uses ssp_clk from FPGA 
 //  -------------------------------------------------------------------------
-void StartCountSspClk()
-{
+void StartCountSspClk() {
 	AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC0) | (1 << AT91C_ID_TC1) | (1 << AT91C_ID_TC2);  // Enable Clock to all timers
 	AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_TIOA1 		// XC0 Clock = TIOA1
 							| AT91C_TCB_TC1XC1S_NONE 		// XC1 Clock = none
@@ -398,17 +408,17 @@ void StartCountSspClk()
 	AT91C_BASE_TC2->TC_CMR = AT91C_TC_CLKS_XC2	 			// TC2 clock = XC2 clock = TIOA0
 							| AT91C_TC_WAVE 				// Waveform Mode
 							| AT91C_TC_WAVESEL_UP;	 		// just count
-	
-	AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN;				// enable TC0
-	AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN;				// enable TC1
-	AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKEN;				// enable TC2
 
-	//
-	// synchronize the counter with the ssp_frame signal. Note: FPGA must be in any iso14446 mode, otherwise the frame signal would not be present 
-	//
+	AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;				// enable and reset TC0
+	AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;				// enable and reset TC1
+	AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;				// enable and reset TC2
+
+	// synchronize the counter with the ssp_frame signal. 
+	// Note: FPGA must be in any iso14443 mode, otherwise the frame signal would not be present 
 	while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME)); 	// wait for ssp_frame to go high (start of frame)
 	while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME); 		// wait for ssp_frame to be low
 	while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)); 	// wait for ssp_clk to go high
+
 	// note: up to now two ssp_clk rising edges have passed since the rising edge of ssp_frame
 	// it is now safe to assert a sync signal. This sets all timers to 0 on next active clock edge
 	AT91C_BASE_TCB->TCB_BCR = 1;							// assert Sync (set all timers to 0 on next active clock edge)
@@ -416,9 +426,16 @@ void StartCountSspClk()
 	// at the next (4th) ssp_clk rising edge, TC0 (the low word of our counter) will be reset. From now on,
 	// whenever the last three bits of our counter go 0, we can be sure to be in the middle of a frame transfer.
 	// (just started with the transfer of the 4th Bit).
-	// The high word of the counter (TC2) will not reset until the low word (TC0) overflows. Therefore need to wait quite some time before
-	// we can use the counter.
-	while (AT91C_BASE_TC0->TC_CV < 0xFFF0);
+
+	// The high word of the counter (TC2) will not reset until the low word (TC0) overflows. 
+	// Therefore need to wait quite some time before we can use the counter.
+	while (AT91C_BASE_TC2->TC_CV >= 1);
+}
+void ResetSspClk(void) {	
+	//enable clock of timer and software trigger
+	AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
+	AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
+	AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
 }
 
 uint32_t RAMFUNC GetCountSspClk(){