X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/proxmark3-svn/blobdiff_plain/f121b478a11894a42f0fdab127974e1e7d521cc3..76471e5d1734786f6095c0b689fa49c5f6e92136:/armsrc/lfops.c?ds=sidebyside

diff --git a/armsrc/lfops.c b/armsrc/lfops.c
index 1f1e48ee..9290007c 100644
--- a/armsrc/lfops.c
+++ b/armsrc/lfops.c
@@ -66,13 +66,13 @@ void ModThenAcquireRawAdcSamples125k(uint32_t delay_off, uint32_t periods, uint3
 		FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
 		LED_D_ON();
 		if(*(command++) == '0')
-			SpinDelayUs(period_0);
+			SpinDelayUs(period_0);	// ICEMAN:  problem with (us) clock is  21.3us increments
 		else
-			SpinDelayUs(period_1);
+			SpinDelayUs(period_1);	// ICEMAN:  problem with (us) clock is  21.3us increments
 	}
 	FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
 	LED_D_OFF();
-	SpinDelayUs(delay_off);
+	SpinDelayUs(delay_off);	// ICEMAN:  problem with (us) clock is  21.3us increments
 	FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
 	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
 
@@ -228,17 +228,17 @@ void WriteTIbyte(uint8_t b)
 		if (b&(1<<i)) {
 			// stop modulating antenna
 			LOW(GPIO_SSC_DOUT);
-			SpinDelayUs(1000);
+			SpinDelayUs(1000);	// ICEMAN:  problem with (us) clock is  21.3us increments
 			// modulate antenna
 			HIGH(GPIO_SSC_DOUT);
-			SpinDelayUs(1000);
+			SpinDelayUs(1000);	// ICEMAN:  problem with (us) clock is  21.3us increments
 		} else {
 			// stop modulating antenna
 			LOW(GPIO_SSC_DOUT);
-			SpinDelayUs(300);
+			SpinDelayUs(300);	// ICEMAN:  problem with (us) clock is  21.3us increments
 			// modulate antenna
 			HIGH(GPIO_SSC_DOUT);
-			SpinDelayUs(1700);
+			SpinDelayUs(1700);	// ICEMAN:  problem with (us) clock is  21.3us increments
 		}
 	}
 }
@@ -437,7 +437,7 @@ void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
 			if (gap) {
 				WDT_HIT();
 				SHORT_COIL();
-				SpinDelayUs(gap);				
+				SpinDelayUs(gap);	// ICEMAN:  problem with (us) clock is  21.3us increments
 			}
 		}
 	}
@@ -1116,7 +1116,7 @@ void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
  * Q5 tags seems to have issues when these values changes. 
  */
 
-#define START_GAP 31*8 // was 250 // SPEC:  1*8 to 50*8 - typ 15*8 (or 15fc)
+#define START_GAP 50*8 // was 250 // SPEC:  1*8 to 50*8 - typ 15*8 (or 15fc)
 #define WRITE_GAP 20*8 // was 160 // SPEC:  1*8 to 20*8 - typ 10*8 (or 10fc)
 #define WRITE_0   18*8 // was 144 // SPEC: 16*8 to 32*8 - typ 24*8 (or 24fc)
 #define WRITE_1   50*8 // was 400 // SPEC: 48*8 to 64*8 - typ 56*8 (or 56fc)  432 for T55x7; 448 for E5550
@@ -1144,7 +1144,7 @@ void TurnReadLFOn(int delay) {
 	//int adcval = ((MAX_ADC_LF_VOLTAGE * AvgAdc(ADC_CHAN_LF)) >> 10);
 	// where to save it
 	
-	SpinDelayUs(delay);
+	SpinDelayCountUs(delay);	// ICEMAN:  problem with (us) clock is  21.3us increments
 }
 
 // Write one bit to card
@@ -1154,7 +1154,7 @@ void T55xxWriteBit(int bit) {
 	else
 		TurnReadLFOn(WRITE_1);
 	FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
-	SpinDelayUs(WRITE_GAP);
+	SpinDelayCountUs(WRITE_GAP);	// ICEMAN:  problem with (us) clock is  21.3us increments
 }
 
 // Send T5577 reset command then read stream (see if we can identify the start of the stream)
@@ -1168,7 +1168,7 @@ void T55xxResetRead(void) {
 
 	// Trigger T55x7 in mode.
 	FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
-	SpinDelayUs(START_GAP);
+	SpinDelayCountUs(START_GAP);	// ICEMAN:  problem with (us) clock is  21.3us increments
 
 	// reset tag - op code 00
 	T55xxWriteBit(0);
@@ -1198,7 +1198,7 @@ void T55xxWriteBlockExt(uint32_t Data, uint8_t Block, uint32_t Pwd, uint8_t arg)
 	
 	// Trigger T55x7 in mode.
 	FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
-	SpinDelayUs(START_GAP);
+	SpinDelayCountUs(START_GAP);	// ICEMAN:  problem with (us) clock is  21.3us increments
 
 	// Opcode 10
 	T55xxWriteBit(1);
@@ -1247,17 +1247,18 @@ void T55xxReadBlock(uint16_t arg0, uint8_t Block, uint32_t Pwd) {
 	bool RegReadMode = (Block == 0xFF);
 	
 	//clear buffer now so it does not interfere with timing later
-	BigBuf_Clear_ext(false);
+	BigBuf_Clear_keep_EM();
 
 	//make sure block is at max 7
 	Block &= 0x7;
 
 	// Set up FPGA, 125kHz to power up the tag
 	LFSetupFPGAForADC(95, true);
+	SpinDelay(3);
 	
 	// Trigger T55x7 Direct Access Mode with start gap
 	FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
-	SpinDelayUs(START_GAP);
+	SpinDelayCountUs(START_GAP);	// ICEMAN:  problem with (us) clock is  21.3us increments
 	
 	// Opcode 1[page]
 	T55xxWriteBit(1);
@@ -1273,8 +1274,8 @@ void T55xxReadBlock(uint16_t arg0, uint8_t Block, uint32_t Pwd) {
 	
 	// Send Block number (if direct access mode)
 	if (!RegReadMode)
-	for (i = 0x04; i != 0; i >>= 1)
-		T55xxWriteBit(Block & i);
+		for (i = 0x04; i != 0; i >>= 1)
+			T55xxWriteBit(Block & i);
 
 	// Turn field on to read the response
 	TurnReadLFOn(READ_GAP);
@@ -1297,7 +1298,7 @@ void T55xxWakeUp(uint32_t Pwd){
 	
 	// Trigger T55x7 Direct Access Mode
 	FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
-	SpinDelayUs(START_GAP);
+	SpinDelayCountUs(START_GAP);	// ICEMAN:  problem with (us) clock is  21.3us increments
 	
 	// Opcode 10
 	T55xxWriteBit(1);
@@ -1628,20 +1629,20 @@ void SendForward(uint8_t fwd_bit_count) {
 	fwd_bit_sz--; //prepare next bit modulation
 	fwd_write_ptr++;
 	FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
-	SpinDelayUs(55*8); //55 cycles off (8us each)for 4305
+	SpinDelayUs(55*8); //55 cycles off (8us each)for 4305	// ICEMAN:  problem with (us) clock is  21.3us increments
 	FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
-	SpinDelayUs(16*8); //16 cycles on (8us each)
+	SpinDelayUs(16*8); //16 cycles on (8us each)	// ICEMAN:  problem with (us) clock is  21.3us increments
 
 	// now start writting
 	while(fwd_bit_sz-- > 0) { //prepare next bit modulation
 		if(((*fwd_write_ptr++) & 1) == 1)
-			SpinDelayUs(32*8); //32 cycles at 125Khz (8us each)
+			SpinDelayUs(32*8); //32 cycles at 125Khz (8us each)	// ICEMAN:  problem with (us) clock is  21.3us increments
 		else {
 			//These timings work for 4469/4269/4305 (with the 55*8 above)
 			FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
-			SpinDelayUs(23*8); //16-4 cycles off (8us each)
+			SpinDelayUs(23*8); //16-4 cycles off (8us each)	// ICEMAN:  problem with (us) clock is  21.3us increments
 			FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
-			SpinDelayUs(9*8); //16 cycles on (8us each)
+			SpinDelayUs(9*8); //16 cycles on (8us each)	// ICEMAN:  problem with (us) clock is  21.3us increments
 		}
 	}
 }