X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/proxmark3-svn/blobdiff_plain/f53020e729d583f7975095ca7b4b467741d99edb..6de14cec0e6914b3c881884d3582a32a551439b1:/armsrc/iso14443b.c diff --git a/armsrc/iso14443b.c b/armsrc/iso14443b.c index 67e4ccdd..ee7f18f2 100644 --- a/armsrc/iso14443b.c +++ b/armsrc/iso14443b.c @@ -334,6 +334,10 @@ void SimulateIso14443bTag(void) 0x00, 0x21, 0x85, 0x5e, 0xd7 }; + uint8_t parity[MAX_PARITY_SIZE]; + + FpgaDownloadAndGo(FPGA_BITSTREAM_HF); + clear_trace(); set_tracing(TRUE); @@ -348,8 +352,6 @@ void SimulateIso14443bTag(void) uint16_t len; uint16_t cmdsRecvd = 0; - FpgaDownloadAndGo(FPGA_BITSTREAM_HF); - // prepare the (only one) tag answer: CodeIso14443bAsTag(response1, sizeof(response1)); uint8_t *resp1Code = BigBuf_malloc(ToSendMax); @@ -370,7 +372,6 @@ void SimulateIso14443bTag(void) } if (tracing) { - uint8_t parity[MAX_PARITY_SIZE]; LogTrace(receivedCmd, len, 0, 0, parity, TRUE); } @@ -411,32 +412,41 @@ void SimulateIso14443bTag(void) AT91C_BASE_SSC->SSC_THR = 0xff; FpgaSetupSsc(); + uint8_t c; + // clear receiving shift register and holding register + while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY)); + c = AT91C_BASE_SSC->SSC_RHR; (void) c; + while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY)); + c = AT91C_BASE_SSC->SSC_RHR; (void) c; + + // Clear TXRDY: + AT91C_BASE_SSC->SSC_THR = 0x00; + // Transmit the response. + uint16_t FpgaSendQueueDelay = 0; uint16_t i = 0; - for(;;) { + for(;i < respCodeLen; ) { if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) { - uint8_t b = respCode[i]; - - AT91C_BASE_SSC->SSC_THR = b; - - i++; - if(i > respCodeLen) { - break; - } + AT91C_BASE_SSC->SSC_THR = respCode[i++]; + FpgaSendQueueDelay = (uint8_t)AT91C_BASE_SSC->SSC_RHR; } - if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) { - volatile uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR; - (void)b; + if(BUTTON_PRESS()) break; + } + + // Ensure that the FPGA Delay Queue is empty before we switch to TAGSIM_LISTEN again: + uint8_t fpga_queued_bits = FpgaSendQueueDelay >> 3; + for (i = 0; i <= fpga_queued_bits/8 + 1; ) { + if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) { + AT91C_BASE_SSC->SSC_THR = 0x00; + FpgaSendQueueDelay = (uint8_t)AT91C_BASE_SSC->SSC_RHR; + i++; } } // trace the response: - if (tracing) { - uint8_t parity[MAX_PARITY_SIZE]; - LogTrace(resp, respLen, 0, 0, parity, FALSE); - } - + if (tracing) LogTrace(resp, respLen, 0, 0, parity, FALSE); } + //FpgaDisableSscDma(); } //============================================================================= @@ -715,13 +725,13 @@ static void GetSamplesFor14443bDemod(int n, bool quiet) BigBuf_free(); // The response (tag -> reader) that we're receiving. - uint8_t *receivedResponse = BigBuf_malloc(MAX_FRAME_SIZE); + uint8_t *resp = BigBuf_malloc(MAX_FRAME_SIZE); // The DMA buffer, used to stream samples from the FPGA int8_t *dmaBuf = (int8_t*) BigBuf_malloc(ISO14443B_DMA_BUFFER_SIZE); // Set up the demodulator for tag -> reader responses. - DemodInit(receivedResponse); + DemodInit(resp); // Setup and start DMA. FpgaSetupSscDma((uint8_t*) dmaBuf, ISO14443B_DMA_BUFFER_SIZE); @@ -733,6 +743,7 @@ static void GetSamplesFor14443bDemod(int n, bool quiet) LED_D_ON(); // And put the FPGA in the appropriate mode FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_848_KHZ); + SpinDelayUs(151); // T0 time between reader send, tag answer. 151us. for(;;) { int behindBy = lastRxCounter - AT91C_BASE_PDC_SSC->PDC_RCR; @@ -908,12 +919,14 @@ static void CodeAndTransmit14443bAsReader(const uint8_t *cmd, int len) //----------------------------------------------------------------------------- void ReadSTMemoryIso14443b(uint32_t dwLast) { + FpgaDownloadAndGo(FPGA_BITSTREAM_HF); + BigBuf_free(); + clear_trace(); set_tracing(TRUE); uint8_t i = 0x00; - FpgaDownloadAndGo(FPGA_BITSTREAM_HF); // Make sure that we start from off, since the tags are stateful; // confusing things will happen if we don't reset them between reads. LED_D_OFF(); @@ -1014,9 +1027,10 @@ void ReadSTMemoryIso14443b(uint32_t dwLast) // Now print out the memory location: Dbprintf("Address=%02x, Contents=%08x, CRC=%04x", i, (Demod.output[3]<<24) + (Demod.output[2]<<16) + (Demod.output[1]<<8) + Demod.output[0], - (Demod.output[4]<<8)+Demod.output[5] - ); - if (i == 0xff) break; + (Demod.output[4]<<8)+Demod.output[5]); + if (i == 0xff) { + break; + } i++; } } @@ -1090,9 +1104,6 @@ void RAMFUNC SnoopIso14443b(void) bool TagIsActive = FALSE; bool ReaderIsActive = FALSE; - bool TagIsActive = FALSE; - bool ReaderIsActive = FALSE; - // And now we loop, receiving samples. for(;;) { int behindBy = (lastRxCounter - AT91C_BASE_PDC_SSC->PDC_RCR) & @@ -1116,10 +1127,6 @@ void RAMFUNC SnoopIso14443b(void) if(behindBy > (9*ISO14443B_DMA_BUFFER_SIZE/10)) { // TODO: understand whether we can increase/decrease as we want or not? Dbprintf("blew circular buffer! behindBy=%d", behindBy); break; - WDT_HIT(); - if(behindBy > (9*DMA_BUFFER_SIZE/10)) { // TODO: understand whether we can increase/decrease as we want or not? - Dbprintf("blew circular buffer! behindBy=%d", behindBy); - break; } if(!tracing) { DbpString("Reached trace limit"); @@ -1163,8 +1170,8 @@ void RAMFUNC SnoopIso14443b(void) //Use samples as a time measurement if(tracing) { - uint8_t parity[MAX_PARITY_SIZE]; - LogTrace(Demod.output, Demod.len, samples, samples, parity, FALSE); + //uint8_t parity[MAX_PARITY_SIZE]; + LogTrace(Demod.output, Demod.len, samples, samples, parity, FALSE); } triggered = TRUE; @@ -1203,12 +1210,16 @@ void RAMFUNC SnoopIso14443b(void) void SendRawCommand14443B(uint32_t datalen, uint32_t recv, uint8_t powerfield, uint8_t data[]) { FpgaDownloadAndGo(FPGA_BITSTREAM_HF); + BigBuf_free(); SetAdcMuxFor(GPIO_MUXSEL_HIPKD); FpgaSetupSsc(); - set_tracing(TRUE); - - CodeAndTransmit14443bAsReader(data, datalen); + if ( datalen == 0 && recv == 0 && powerfield == 0){ + clear_trace(); + } else { + set_tracing(TRUE); + CodeAndTransmit14443bAsReader(data, datalen); + } if(recv) { GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, TRUE); @@ -1220,5 +1231,7 @@ void SendRawCommand14443B(uint32_t datalen, uint32_t recv, uint8_t powerfield, u FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); LED_D_OFF(); } + + FpgaDisableSscDma(); }