git.zerfleddert.de Git - proxmark3-svn/commit

]> git.zerfleddert.de Git - proxmark3-svn/commit - fpga/hi_sniffer.v

author	pwpiwi <pwpiwi@users.noreply.github.com>
	Sun, 24 Mar 2019 17:11:41 +0000 (18:11 +0100)
committer	GitHub <noreply@github.com>
	Sun, 24 Mar 2019 17:11:41 +0000 (18:11 +0100)
commit	5ea2a24839c71ba6e58af937a392a6204b8b4696
tree	93400aa632102d874504de570c3053ef0e183043	tree \| snapshot
parent	ca8a3478d949a03953129ec34d209a9c80079252	commit \| diff

FPGA changes (#803)

* merge hf_rx_xcorr and hf_tx modes into one module with common ssp_clk and ssp_frame
* get rid of most of the warnings when compiling the HF verilog sources
* refactoring the constants in Verilog sources

18 files changed:

armsrc/appmain.c		diff \| blob \| blame \| history
armsrc/fpgaloader.c		diff \| blob \| blame \| history
armsrc/fpgaloader.h		diff \| blob \| blame \| history
armsrc/iso14443b.c		diff \| blob \| blame \| history
armsrc/iso14443b.h		diff \| blob \| blame \| history
armsrc/iso15693.c		diff \| blob \| blame \| history
armsrc/legicrf.c		diff \| blob \| blame \| history
fpga/Makefile		diff \| blob \| blame \| history
fpga/fpga.ucf		diff \| blob \| blame \| history
fpga/fpga_hf.bit		diff \| blob \| blame \| history
fpga/fpga_hf.v		diff \| blob \| blame \| history
fpga/hi_get_trace.v		diff \| blob \| blame \| history
fpga/hi_iso14443a.v		diff \| blob \| blame \| history
fpga/hi_read_rx_xcorr.v	[deleted file]	blob \| blame \| history
fpga/hi_read_tx.v	[deleted file]	blob \| blame \| history
fpga/hi_reader.v	[new file with mode: 0644]	blob
fpga/hi_simulate.v		diff \| blob \| blame \| history
fpga/hi_sniffer.v		diff \| blob \| blame \| history

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