... sensitive routines
see http://www.proxmark.org/forum/viewtopic.php?id=2820
Dbprintf("Buffer cleared (%i bytes)",BIGBUF_SIZE);
}
Dbprintf("Buffer cleared (%i bytes)",BIGBUF_SIZE);
}
+void BigBuf_Clear_keep_EM(void)
+{
+ memset(BigBuf,0,BigBuf_hi);
+}
// allocate a chunk of memory from BigBuf. We allocate high memory first. The unallocated memory
// at the beginning of BigBuf is always for traces/samples
// allocate a chunk of memory from BigBuf. We allocate high memory first. The unallocated memory
// at the beginning of BigBuf is always for traces/samples
extern uint16_t BigBuf_max_traceLen(void);
extern void BigBuf_Clear(void);
extern void BigBuf_Clear_ext(bool verbose);
extern uint16_t BigBuf_max_traceLen(void);
extern void BigBuf_Clear(void);
extern void BigBuf_Clear_ext(bool verbose);
+extern void BigBuf_Clear_keep_EM(void);
extern uint8_t *BigBuf_malloc(uint16_t);
extern void BigBuf_free(void);
extern void BigBuf_free_keep_EM(void);
extern uint8_t *BigBuf_malloc(uint16_t);
extern void BigBuf_free(void);
extern void BigBuf_free_keep_EM(void);
sample_config sc = { 0,0,1, divisor_used, 0};
setSamplingConfig(&sc);
sample_config sc = { 0,0,1, divisor_used, 0};
setSamplingConfig(&sc);
+ //clear read buffer
+ BigBuf_Clear_keep_EM(void);
/* Make sure the tag is reset */
FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
/* Make sure the tag is reset */
FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
// Configure to go in 125Khz listen mode
LFSetupFPGAForADC(95, true);
// Configure to go in 125Khz listen mode
LFSetupFPGAForADC(95, true);
+ //clear read buffer
+ BigBuf_Clear_keep_EM(void);
+
while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
WDT_HIT();
while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
WDT_HIT();
uint8_t *dest = BigBuf_get_addr();
size_t size;
int idx=0;
uint8_t *dest = BigBuf_get_addr();
size_t size;
int idx=0;
+ //clear read buffer
+ BigBuf_Clear_keep_EM(void);
// Configure to go in 125Khz listen mode
LFSetupFPGAForADC(95, true);
// Configure to go in 125Khz listen mode
LFSetupFPGAForADC(95, true);
int clk=0, invert=0, errCnt=0, maxErr=20;
uint32_t hi=0;
uint64_t lo=0;
int clk=0, invert=0, errCnt=0, maxErr=20;
uint32_t hi=0;
uint64_t lo=0;
+ //clear read buffer
+ BigBuf_Clear_keep_EM(void);
// Configure to go in 125Khz listen mode
LFSetupFPGAForADC(95, true);
// Configure to go in 125Khz listen mode
LFSetupFPGAForADC(95, true);
uint8_t version=0;
uint8_t facilitycode=0;
uint16_t number=0;
uint8_t version=0;
uint8_t facilitycode=0;
uint16_t number=0;
+ //clear read buffer
+ BigBuf_Clear_keep_EM(void);
// Configure to go in 125Khz listen mode
LFSetupFPGAForADC(95, true);
// Configure to go in 125Khz listen mode
LFSetupFPGAForADC(95, true);
uint8_t *dest = BigBuf_get_addr();
int bufsize = BigBuf_max_traceLen();
uint8_t *dest = BigBuf_get_addr();
int bufsize = BigBuf_max_traceLen();
- memset(dest, 0, bufsize);
+ //memset(dest, 0, bufsize); //creates issues with cmdread (marshmellow)
if(bits_per_sample < 1) bits_per_sample = 1;
if(bits_per_sample > 8) bits_per_sample = 8;
if(bits_per_sample < 1) bits_per_sample = 1;
if(bits_per_sample > 8) bits_per_sample = 8;
int num_blocks = 0;
int lmin=128, lmax=128;
uint8_t dir;
int num_blocks = 0;
int lmin=128, lmax=128;
uint8_t dir;
+ //clear read buffer
+ BigBuf_Clear_keep_EM(void);
LFSetupFPGAForADC(95, true);
DoAcquisition_default(0, true);
LFSetupFPGAForADC(95, true);
DoAcquisition_default(0, true);