From: Timo Hirvonen <timhir@gmail.com>
Date: Mon, 6 Mar 2017 09:39:12 +0000 (+0200)
Subject: Improved logic for determining the correct Frame Delay Time (FDT) value based on... 
X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/proxmark3-svn/commitdiff_plain/17ab9dcca02ae85e1f31b30eb74efec41a187917

Improved logic for determining the correct Frame Delay Time (FDT) value based on the last bit transmitted by the PCD
---

diff --git a/armsrc/iso14443a.c b/armsrc/iso14443a.c
index 76a76673..91a1a0f8 100644
--- a/armsrc/iso14443a.c
+++ b/armsrc/iso14443a.c
@@ -1604,9 +1604,16 @@ int EmSendCmd14443aRaw(uint8_t *resp, uint16_t respLen, bool correctionNeeded) {
 	// Modulate Manchester
 	FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_MOD);
 
-	// include correction bit if necessary
-	if (Uart.parityBits & 0x01) {
-		correctionNeeded = TRUE;
+	// Include correction bit if necessary
+	if (Uart.bitCount == 7)
+	{
+		// Short tags (7 bits) don't have parity, determine the correct value from MSB
+		correctionNeeded = Uart.output[0] & 0x40;
+	}
+	else
+	{
+		// The parity bits are left-aligned
+		correctionNeeded = Uart.parity[(Uart.len-1)/8] & (0x80 >> ((Uart.len-1) & 7));
 	}
 	// 1236, so correction bit needed
 	i = (correctionNeeded) ? 0 : 1;