From: AntiCat <contiki@anticat.ch>
Date: Sun, 9 Sep 2018 14:40:20 +0000 (+0200)
Subject: Legic Tag Simulator (#666)
X-Git-Tag: v3.1.0~22
X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/proxmark3-svn/commitdiff_plain/1b902aa01afa39ff413b74142cd56d092b4500a1?ds=inline;hp=1b902aa01afa39ff413b74142cd56d092b4500a1

Legic Tag Simulator (#666)

* FPGA Hi-Simulate: Formatted code
* FPGA Hi-Simulate: Fixed documantation
* FPGA Hi-Simulate: Freed up 4 LUTs
* FPGA Hi-Simulate: Added 212kHz SSP-Clock option
* Legic: Moved card simulator into separate file & cleaned interface.
Reader and card simulation have almost no common code. Moreover the sim
uses an SSP Clock at 212kHz for all timings to prevent any drifting from
the PRNG. This clock speed is not available in reader simulation mode (SSP
runs at up to 3.4MHz, and changes speed between TX and RX). For these
reasons having the code in separate files makes it significantly cleaner.
* Legic: Implemented RX and TX for card simulation
* Legic: Implemented setup phase for card simulation
* Legic: Implemented read command for card simulation
* Legic: Implemented write command for card simulation
---