From: iceman1001 <iceman@iuse.se>
Date: Sun, 10 Apr 2016 10:55:18 +0000 (+0200)
Subject: CHG: some textual change and some syntax suger changes.
X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/proxmark3-svn/commitdiff_plain/5eceba292f639ba9ff50a2e85d2358e93cfcd541?ds=inline

CHG: some textual change and some syntax suger changes.
---

diff --git a/armsrc/crapto1.c b/armsrc/crapto1.c
index a6b6da4d..fcfd0b4d 100644
--- a/armsrc/crapto1.c
+++ b/armsrc/crapto1.c
@@ -520,9 +520,8 @@ struct Crypto1State* lfsr_common_prefix(uint32_t pfx, uint32_t rr, uint8_t ks[8]
 	s = statelist = malloc((sizeof *statelist) << 21);
 	if(!s || !odd || !even) {
 		free(statelist);
-		free(odd);
-		free(even);
-		return 0;
+		statelist = 0;
+		goto out;
 	}
 
 	for(o = odd; *o + 1; ++o)
@@ -534,7 +533,7 @@ struct Crypto1State* lfsr_common_prefix(uint32_t pfx, uint32_t rr, uint8_t ks[8]
 			}
 
 	s->odd = s->even = 0;
-
+out:
 	free(odd);
 	free(even);
 	return statelist;
diff --git a/armsrc/fpgaloader.h b/armsrc/fpgaloader.h
index 35f7e37c..5c0f802e 100644
--- a/armsrc/fpgaloader.h
+++ b/armsrc/fpgaloader.h
@@ -64,6 +64,7 @@ void SetAdcMuxFor(uint32_t whichGpio);
 #define FPGA_HF_SIMULATOR_MODULATE_212K				(2<<0)
 #define FPGA_HF_SIMULATOR_MODULATE_424K				(4<<0)
 #define FPGA_HF_SIMULATOR_MODULATE_424K_8BIT		0x5//101
+//  no 848K 
 
 // Options for ISO14443A
 #define FPGA_HF_ISO14443A_SNIFFER					(0<<0)
diff --git a/armsrc/hfsnoop.c b/armsrc/hfsnoop.c
index 945809ce..4af8522a 100644
--- a/armsrc/hfsnoop.c
+++ b/armsrc/hfsnoop.c
@@ -19,7 +19,7 @@ static void RAMFUNC optimizedSnoop(void)
 		if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY)
 		{
 			*dest = (uint16_t)(AT91C_BASE_SSC->SSC_RHR);
-			dest = dest + 1;
+			++dest;
 		}
 	}
 	//Resetting Frame mode (First set in fpgaloader.c)
@@ -54,6 +54,7 @@ void HfSnoop(int samplesToSkip, int triggersToSkip)
 			r = MAX(r & 0xff, r >> 8); 
 			if (r >= 240) 
 			{
+				
 				if (++trigger_cnt > triggersToSkip) {
 				break;
 			} 
@@ -64,9 +65,9 @@ void HfSnoop(int samplesToSkip, int triggersToSkip)
 	if(!BUTTON_PRESS()) {
 		int waitcount = samplesToSkip; // lets wait 40000 ticks of pck0
 		while(waitcount != 0) {
-			if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
-				waitcount--;
-			}
+			
+			if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY))
+				--waitcount;
 		}
 		optimizedSnoop();
 		Dbprintf("Trigger kicked! Value: %d, Dumping Samples Hispeed now.", r);
diff --git a/armsrc/iclass.c b/armsrc/iclass.c
index dcb672e7..134e7a5e 100644
--- a/armsrc/iclass.c
+++ b/armsrc/iclass.c
@@ -919,7 +919,7 @@ static void CodeIClassTagAnswer(const uint8_t *cmd, int len)
 	 * The mode FPGA_HF_SIMULATOR_MODULATE_424K_8BIT which we use to simulate tag,
 	 * works like this.
 	 * - A 1-bit input to the FPGA becomes 8 pulses on 423.5kHz (fc/32) (18.88us).
-	 * - A 0-bit inptu to the FPGA becomes an unmodulated time of 18.88us
+	 * - A 0-bit input to the FPGA becomes an unmodulated time of 18.88us
 	 *
 	 * In this mode the SOF can be written as 00011101 = 0x1D
 	 * The EOF can be written as 10111000 = 0xb8
@@ -1384,6 +1384,7 @@ static int SendIClassAnswer(uint8_t *resp, int respLen, int delay)
 static void TransmitIClassCommand(const uint8_t *cmd, int len, int *samples, int *wait)
 {
 	int c;
+	volatile uint32_t r;
 	FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD);
 	AT91C_BASE_SSC->SSC_THR = 0x00;
 	FpgaSetupSsc();
@@ -1397,7 +1398,7 @@ static void TransmitIClassCommand(const uint8_t *cmd, int len, int *samples, int
 				c++;
 			}
 			if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
-				volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;
+				r = AT91C_BASE_SSC->SSC_RHR;
 				(void)r;
 			}
 			WDT_HIT();
@@ -1408,36 +1409,36 @@ static void TransmitIClassCommand(const uint8_t *cmd, int len, int *samples, int
 	uint8_t sendbyte;
 	bool firstpart = TRUE;
 	c = 0;
-  for(;;) {
-    if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
+	for(;;) {
+		if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
 
-      // DOUBLE THE SAMPLES!
-      if(firstpart) {
-	sendbyte = (cmd[c] & 0xf0) | (cmd[c] >> 4); 
-      }
-      else {
-	sendbyte = (cmd[c] & 0x0f) | (cmd[c] << 4);
-        c++;
-      }
-      if(sendbyte == 0xff) {
-	sendbyte = 0xfe;
-      }
-      AT91C_BASE_SSC->SSC_THR = sendbyte;
-      firstpart = !firstpart;
+			// DOUBLE THE SAMPLES!
+			if(firstpart) {
+				sendbyte = (cmd[c] & 0xf0) | (cmd[c] >> 4); 
+			}
+			else {
+				sendbyte = (cmd[c] & 0x0f) | (cmd[c] << 4);
+				c++;
+			}
 
-      if(c >= len) {
-        break;
-      }
-    }
-    if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
-      volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;
-      (void)r;
-    }
-    WDT_HIT();
-  }
-  if (samples && wait) *samples = (c + *wait) << 3;
-}
+			if(sendbyte == 0xff)
+				sendbyte = 0xfe;
+
+			AT91C_BASE_SSC->SSC_THR = sendbyte;
+			firstpart = !firstpart;
 
+			if(c >= len) break;
+
+		}
+		if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
+			r = AT91C_BASE_SSC->SSC_RHR;
+			(void)r;
+		}
+		
+		WDT_HIT();
+	}
+	if (samples && wait) *samples = (c + *wait) << 3;
+}
 
 //-----------------------------------------------------------------------------
 // Prepare iClass reader command to send to FPGA