From: henryk@ploetzli.ch Date: Mon, 12 Oct 2009 07:46:03 +0000 (+0000) Subject: Add HF simulator modulation mode for 212kHz subcarrier X-Git-Tag: v1.0.0~463 X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/proxmark3-svn/commitdiff_plain/ecf53cb2158e65f3b6f44788c80deb2235fb0ba9 Add HF simulator modulation mode for 212kHz subcarrier --- diff --git a/armsrc/apps.h b/armsrc/apps.h index bf45407f..040737e7 100644 --- a/armsrc/apps.h +++ b/armsrc/apps.h @@ -56,6 +56,7 @@ void SetAdcMuxFor(DWORD whichGpio); // Options for the HF simulated tag, how to modulate #define FPGA_HF_SIMULATOR_NO_MODULATION (0<<0) #define FPGA_HF_SIMULATOR_MODULATE_BPSK (1<<0) +#define FPGA_HF_SIMULATOR_MODULATE_212K (2<<0) // Options for ISO14443A #define FPGA_HF_ISO14443A_SNIFFER (0<<0) #define FPGA_HF_ISO14443A_TAGSIM_LISTEN (1<<0) diff --git a/fpga/fpga.bit b/fpga/fpga.bit index 503f041f..a9b03e13 100644 Binary files a/fpga/fpga.bit and b/fpga/fpga.bit differ diff --git a/fpga/hi_simulate.v b/fpga/hi_simulate.v index d0a71176..05662e53 100644 --- a/fpga/hi_simulate.v +++ b/fpga/hi_simulate.v @@ -51,7 +51,8 @@ begin end // Divide 13.56 MHz by 32 to produce the SSP_CLK -reg [4:0] ssp_clk_divider; +// The register is bigger to allow higher division factors of up to /128 +reg [6:0] ssp_clk_divider; always @(posedge adc_clk) ssp_clk_divider <= (ssp_clk_divider + 1); assign ssp_clk = ssp_clk_divider[4]; @@ -87,6 +88,8 @@ always @(mod_type or ssp_clk or ssp_dout) modulating_carrier <= 1'b0; // no modulation else if(mod_type == 3'b001) modulating_carrier <= ssp_dout ^ ssp_clk_divider[3]; // XOR means BPSK + else if(mod_type == 3'b010) + modulating_carrier <= ssp_dout & ssp_clk_divider[5]; // switch 212kHz subcarrier on/off else modulating_carrier <= 1'b0; // yet unused