[raggedstone] / dhwk / source / Verg_2.vhd

-- J.STELZNER
-- INFORMATIK-3 LABOR
-- 23.08.2006
-- File: VERG_2.VHD

library ieee;
use ieee.std_logic_1164.all;

entity VERG_2 is
        port
        (
                IN_A :in std_logic_vector(1 downto 0);
                IN_B :in std_logic_vector(1 downto 0);
                GLEICH :out std_logic
        );
end entity VERG_2;

architecture VERG_2_DESIGN of VERG_2 is

begin

        process (IN_A,IN_B)
        begin

        if IN_A = IN_B then
                GLEICH <= '1';
        else
                GLEICH <= '0';
        end if;

end process;

end architecture VERG_2_DESIGN;
Commit	Line	Data
696ded12	1	-- J.STELZNER
	2	-- INFORMATIK-3 LABOR
	3	-- 23.08.2006
	4	-- File: VERG_2.VHD
	5
2612d712	6	library ieee;
	7	use ieee.std_logic_1164.all;
	8
	9	entity VERG_2 is
	10	port
	11	(
	12	IN_A :in std_logic_vector(1 downto 0);
	13	IN_B :in std_logic_vector(1 downto 0);
	14	GLEICH :out std_logic
	15	);
	16	end entity VERG_2;
696ded12	17
	18	architecture VERG_2_DESIGN of VERG_2 is
	19
	20	begin
	21
2612d712	22	process (IN_A,IN_B)
2612d712	23	begin
696ded12	24
2612d712	25	if IN_A = IN_B then
	26	GLEICH <= '1';
	27	else
	28	GLEICH <= '0';
	29	end if;
696ded12	30
2612d712	31	end process;
696ded12	32
2612d712	33	end architecture VERG_2_DESIGN;