remove build fifo, ila and icon
[raggedstone] / dhwk / fifo.xco
CommitLineData
12bc1626 1##############################################################
2#
3# Xilinx Core Generator version J.30
4# Date: Sat Mar 10 21:20:43 2007
5#
6##############################################################
7#
8# This file contains the customisation parameters for a
9# Xilinx CORE Generator IP GUI. It is strongly recommended
10# that you do not manually alter this file as it may cause
11# unexpected and unsupported behavior.
12#
13##############################################################
14#
15# BEGIN Project Options
16SET addpads = False
17SET asysymbol = False
18SET busformat = BusFormatAngleBracketNotRipped
19SET createndf = False
20SET designentry = VHDL
21SET device = xc3s1500
22SET devicefamily = spartan3
23SET flowvendor = Other
24SET formalverification = False
25SET foundationsym = False
26SET implementationfiletype = Ngc
27SET package = fg456
28SET removerpms = False
29SET simulationfiles = Behavioral
30SET speedgrade = -4
31SET verilogsim = False
32SET vhdlsim = True
33# END Project Options
34# BEGIN Select
35SELECT Fifo_Generator family Xilinx,_Inc. 3.2
36# END Select
37# BEGIN Parameters
38CSET almost_empty_flag=true
39CSET almost_full_flag=true
40CSET component_name=fifo_generator_v3_2
41CSET data_count=false
42CSET data_count_width=12
43CSET dout_reset_value=0
44CSET empty_threshold_assert_value=2
45CSET empty_threshold_negate_value=3
46CSET fifo_implementation=Common_Clock_Block_RAM
47CSET full_threshold_assert_value=2048
48CSET full_threshold_negate_value=2047
49CSET input_data_width=8
50CSET input_depth=4096
51CSET output_data_width=8
52CSET output_depth=4096
53CSET overflow_flag=false
54CSET overflow_sense=Active_High
55CSET performance_options=Standard_FIFO
56CSET programmable_empty_type=No_Programmable_Empty_Threshold
57CSET programmable_full_type=Single_Programmable_Full_Threshold_Constant
58CSET read_clock_frequency=100
59CSET read_data_count=false
60CSET read_data_count_width=12
61CSET reset_pin=true
62CSET reset_type=Asynchronous_Reset
63CSET underflow_flag=false
64CSET underflow_sense=Active_High
65CSET use_extra_logic=false
66CSET valid_flag=false
67CSET valid_sense=Active_High
68CSET write_acknowledge_flag=false
69CSET write_acknowledge_sense=Active_High
70CSET write_clock_frequency=100
71CSET write_data_count=false
72CSET write_data_count_width=12
73# END Parameters
74GENERATE
75# CRC: c795162c
76
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