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40a1f26c 1//////////////////////////////////////////////////////////////////////
2//// ////
3//// File name "conf_cyc_addr_dec.v" ////
4//// ////
5//// This file is part of the "PCI bridge" project ////
6//// http://www.opencores.org/cores/pci/ ////
7//// ////
8//// Author(s): ////
9//// - Miha Dolenc (mihad@opencores.org) ////
10//// ////
11//// All additional information is avaliable in the README ////
12//// file. ////
13//// ////
14//// ////
15//////////////////////////////////////////////////////////////////////
16//// ////
17//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org ////
18//// ////
19//// This source file may be used and distributed without ////
20//// restriction provided that this copyright statement is not ////
21//// removed from the file and that any derivative work contains ////
22//// the original copyright notice and the associated disclaimer. ////
23//// ////
24//// This source file is free software; you can redistribute it ////
25//// and/or modify it under the terms of the GNU Lesser General ////
26//// Public License as published by the Free Software Foundation; ////
27//// either version 2.1 of the License, or (at your option) any ////
28//// later version. ////
29//// ////
30//// This source is distributed in the hope that it will be ////
31//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
32//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
33//// PURPOSE. See the GNU Lesser General Public License for more ////
34//// details. ////
35//// ////
36//// You should have received a copy of the GNU Lesser General ////
37//// Public License along with this source; if not, download it ////
38//// from http://www.opencores.org/lgpl.shtml ////
39//// ////
40//////////////////////////////////////////////////////////////////////
41//
42// CVS Revision History
43//
44// $Log: pci_conf_cyc_addr_dec.v,v $
45// Revision 1.1 2007-03-20 17:50:56 sithglan
46// add shit
47//
48// Revision 1.1 2003/01/27 16:49:31 mihad
49// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
50//
51// Revision 1.3 2002/02/01 15:25:12 mihad
52// Repaired a few bugs, updated specification, added test bench files and design document
53//
54// Revision 1.2 2001/10/05 08:14:28 mihad
55// Updated all files with inclusion of timescale file for simulation purposes.
56//
57// Revision 1.1.1.1 2001/10/02 15:33:46 mihad
58// New project directory structure
59//
60//
61
62
63// module is a simple decoder which decodes device num field of configuration address
64// for type0 configuration cycles. If type 1 configuration cycle is
65// initiated then address goes through unchanged
66
67// synopsys translate_off
68`include "timescale.v"
69// synopsys translate_on
70
71module pci_conf_cyc_addr_dec
72(
73 ccyc_addr_in,
74 ccyc_addr_out
75) ;
76
77input [31:0] ccyc_addr_in ;
78output [31:0] ccyc_addr_out ;
79reg [31:11] ccyc_addr_31_11 ;
80
81// lower 11 address lines are alweys going through unchanged
82assign ccyc_addr_out = {ccyc_addr_31_11, ccyc_addr_in[10:0]} ;
83
84// configuration cycle type indicator
85wire ccyc_type = ccyc_addr_in[0] ;
86
87always@(ccyc_addr_in or ccyc_type)
88begin
89 if (ccyc_type)
90 // type 1 cycle - address goes through unchanged
91 ccyc_addr_31_11 = ccyc_addr_in[31:11] ;
92 else
93 begin
94 // type 0 conf. cycle - decode device number field to appropriate value
95 case (ccyc_addr_in[15:11])
96 5'h00:ccyc_addr_31_11 = 21'h00_0001 ;
97 5'h01:ccyc_addr_31_11 = 21'h00_0002 ;
98 5'h02:ccyc_addr_31_11 = 21'h00_0004 ;
99 5'h03:ccyc_addr_31_11 = 21'h00_0008 ;
100 5'h04:ccyc_addr_31_11 = 21'h00_0010 ;
101 5'h05:ccyc_addr_31_11 = 21'h00_0020 ;
102 5'h06:ccyc_addr_31_11 = 21'h00_0040 ;
103 5'h07:ccyc_addr_31_11 = 21'h00_0080 ;
104 5'h08:ccyc_addr_31_11 = 21'h00_0100 ;
105 5'h09:ccyc_addr_31_11 = 21'h00_0200 ;
106 5'h0A:ccyc_addr_31_11 = 21'h00_0400 ;
107 5'h0B:ccyc_addr_31_11 = 21'h00_0800 ;
108 5'h0C:ccyc_addr_31_11 = 21'h00_1000 ;
109 5'h0D:ccyc_addr_31_11 = 21'h00_2000 ;
110 5'h0E:ccyc_addr_31_11 = 21'h00_4000 ;
111 5'h0F:ccyc_addr_31_11 = 21'h00_8000 ;
112 5'h10:ccyc_addr_31_11 = 21'h01_0000 ;
113 5'h11:ccyc_addr_31_11 = 21'h02_0000 ;
114 5'h12:ccyc_addr_31_11 = 21'h04_0000 ;
115 5'h13:ccyc_addr_31_11 = 21'h08_0000 ;
116 5'h14:ccyc_addr_31_11 = 21'h10_0000 ;
117 default: ccyc_addr_31_11 = 21'h00_0000 ;
118 endcase
119 end
120end
121
122endmodule
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