]> git.zerfleddert.de Git - raggedstone/blame - ethernet/source/pci/pci_irdy_out_crit.v
changes
[raggedstone] / ethernet / source / pci / pci_irdy_out_crit.v
CommitLineData
40a1f26c 1//////////////////////////////////////////////////////////////////////
2//// ////
3//// File name "irdy_out_crit.v" ////
4//// ////
5//// This file is part of the "PCI bridge" project ////
6//// http://www.opencores.org/cores/pci/ ////
7//// ////
8//// Author(s): ////
9//// - Miha Dolenc (mihad@opencores.org) ////
10//// ////
11//// All additional information is avaliable in the README ////
12//// file. ////
13//// ////
14//// ////
15//////////////////////////////////////////////////////////////////////
16//// ////
17//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org ////
18//// ////
19//// This source file may be used and distributed without ////
20//// restriction provided that this copyright statement is not ////
21//// removed from the file and that any derivative work contains ////
22//// the original copyright notice and the associated disclaimer. ////
23//// ////
24//// This source file is free software; you can redistribute it ////
25//// and/or modify it under the terms of the GNU Lesser General ////
26//// Public License as published by the Free Software Foundation; ////
27//// either version 2.1 of the License, or (at your option) any ////
28//// later version. ////
29//// ////
30//// This source is distributed in the hope that it will be ////
31//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
32//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
33//// PURPOSE. See the GNU Lesser General Public License for more ////
34//// details. ////
35//// ////
36//// You should have received a copy of the GNU Lesser General ////
37//// Public License along with this source; if not, download it ////
38//// from http://www.opencores.org/lgpl.shtml ////
39//// ////
40//////////////////////////////////////////////////////////////////////
41//
42// CVS Revision History
43//
44// $Log: pci_irdy_out_crit.v,v $
45// Revision 1.1 2007-03-20 17:50:56 sithglan
46// add shit
47//
48// Revision 1.1 2003/01/27 16:49:31 mihad
49// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
50//
51// Revision 1.3 2002/02/01 15:25:12 mihad
52// Repaired a few bugs, updated specification, added test bench files and design document
53//
54// Revision 1.2 2001/10/05 08:14:28 mihad
55// Updated all files with inclusion of timescale file for simulation purposes.
56//
57// Revision 1.1.1.1 2001/10/02 15:33:46 mihad
58// New project directory structure
59//
60//
61
62// module is used to separate logic which uses criticaly constrained inputs from slower logic.
63// It is used to synthesize critical timing logic separately with faster cells or without optimization
64
65// synopsys translate_off
66`include "timescale.v"
67// synopsys translate_on
68
69// This module is used in master state machine for IRDY output driving
70
71module pci_irdy_out_crit
72(
73 pci_irdy_out,
74 irdy_slow_in,
75 pci_frame_out_in,
76 pci_trdy_in,
77 pci_stop_in
78) ;
79
80output pci_irdy_out ;
81input irdy_slow_in,
82 pci_frame_out_in,
83 pci_trdy_in,
84 pci_stop_in ;
85
86assign pci_irdy_out = irdy_slow_in || (pci_frame_out_in && ~(pci_trdy_in && pci_stop_in)) ;
87
88endmodule
Impressum, Datenschutz