changes
[raggedstone] / heartbeat / source / new_pciregs.vhd
CommitLineData
95764a11 1--+-------------------------------------------------------------------------------------------------+\r
2--| |\r
3--| File: pciregs.vhd |\r
4--| |\r
5--| Project: pci32tlite_oc |\r
6--| |\r
7--| Description: Registros PCI |\r
8--| BAR0 is used externally by decoder. |\r
9--| |\r
10--| +-----------------------------------------------------------------------+ |\r
11--| | PCI CONFIGURATION SPACE REGISTERS | |\r
12--| +-----------------------------------------------------------------------+ |\r
13--| |\r
14--| +-------------------------------------------------------------------+ |\r
15--| | REGISTER | adr(7..2) | offset | Byte Enable | Size | |\r
16--| +-------------------------------------------------------------------+ |\r
17--| | VENDORID | 000000 (r) | 00 | 0/1 | 2 | |\r
18--| +-------------------------------------------------------------------+ |\r
19--| | DERVICEID | 000000 (r) | 02 | 2/3 | 2 | |\r
20--| +-------------------------------------------------------------------+ |\r
21--| | CMD | 000001 (r/w) | 04 | 0/1 | 2 | |\r
22--| +-------------------------------------------------------------------+ |\r
23--| | ST | 000001 (r/w*)| 06 | 2/3 | 2 | |\r
24--| +-------------------------------------------------------------------+ |\r
25--| | REVISIONID | 000010 (r) | 08 | 0 | 1 | |\r
26--| +-------------------------------------------------------------------+ |\r
27--| | CLASSCODE | 000010 (r) | 09 | 1/2/3 | 3 | |\r
28--| +-------------------------------------------------------------------+ |\r
29--| | HEADERTYPE | 000011 (r) | 0E | 2 | 1 | |\r
30--| +-------------------------------------------------------------------+ |\r
31--| | BAR0 | 000100 (r/w) | 10 | 0/1/2/3 | 4 | |\r
32--| +-------------------------------------------------------------------+ |\r
33--| | SUBSYSTEMID | 001011 (r) | 2C | 0/1 | 2 | |\r
34--| +-------------------------------------------------------------------+ |\r
35--| | SUBSYSTEMVID | 001011 (r) | 2E | 0/1 | 2 | |\r
36--| +-------------------------------------------------------------------+ |\r
37--| | INTLINE | 001111 (r/w) | 3C | 0 | 1 | |\r
38--| +-------------------------------------------------------------------+ |\r
39--| | INTPIN | 001111 (r) | 3D | 1 | 1 | |\r
40--| +-------------------------------------------------------------------+ |\r
41--| (w*) Reseteable |\r
42--| |\r
43--| +-----------------------------------------------+ |\r
44--| | VENDORID (r) Vendor ID register | |\r
45--| +-----------------------------------------------+-----------------------+ |\r
46--| | Identifies manufacturer of device. | |\r
47--| | VENDORIDr : vendorID (generic) | |\r
48--| +-----------------------------------------------------------------------+ |\r
49--| |\r
50--| +-----------------------------------------------+ |\r
51--| | DEVICEID (r) Device ID register | |\r
52--| +-----------------------------------------------+-----------------------+ |\r
53--| | Identifies the device. | |\r
54--| | DEVICEIDr : deviceID (generic) | |\r
55--| +-----------------------------------------------------------------------+ |\r
56--| |\r
57--| +-----------------------------------------------+ |\r
58--| | CMD (r/w) CoMmanD register | |\r
59--| +-----------------------------------------------+----------------------------+ |\r
60--| | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SERRENb| (15-8) |\r
61--| +----------------------------------------------------------------------------+ |\r
62--| | 0 | PERRENb| 0 | 0 | 0 | 0 |MEMSPACEENb| 0 | (7-0) |\r
63--| +----------------------------------------------------------------------------+ |\r
64--| | SERRENb : System ERRor ENable (1 = Enabled) | |\r
65--| | PERRENb : Parity ERRor ENable (1 = Enabled) | |\r
66--| | MEMSPACEENb : MEMmory SPACE ENable (1 = Enabled) | |\r
67--| +-----------------------------------------------------------------------+ |\r
68--| |\r
69--| +-----------------------------------------------+ |\r
70--| | ST (r/w*) STatus register | |\r
71--| +-----------------------------------------------+-------------------------+ |\r
72--| | PERRDTb | SERRSIb| -- | -- |TABORTSIb| DEVSELTIMb(1..0)| -- | (15-8) |\r
73--| +-------------------------------------------------------------------------+ |\r
74--| | -- | -- | -- | -- | -- | -- | -- | -- | (7-0) |\r
75--| +-------------------------------------------------------------------------+ |\r
76--| | PERRDTb : Parity ERRor DeTected | |\r
77--| | SERRSIb : System ERRor SIgnaled | |\r
78--| | TABORTSIb : Target ABORT SIgnaled | |\r
79--| +-----------------------------------------------------------------------+ |\r
80--| |\r
81--| +-----------------------------------------------+ |\r
82--| | REVISIONID (r) Revision ID register | |\r
83--| +-----------------------------------------------+-----------------------+ |\r
84--| | Identifies a device revision. | |\r
85--| +-----------------------------------------------------------------------+ |\r
86--| +-----------------------------------------------+ |\r
87--| | CLASSCODE (r) CLASS CODE register | |\r
88--| +-----------------------------------------------+-----------------------+ |\r
89--| | Identifies the generic funtion of the device. | |\r
90--| +-----------------------------------------------------------------------+ |\r
91--| +-----------------------------------------------+ |\r
92--| | HEADERTYPE (r) Header Type register | |\r
93--| +-----------------------------------------------+-----------------------+ |\r
94--| | Identifies the layout of the second part of the predefined header. | |\r
95--| +-----------------------------------------------------------------------+ |\r
96--| |\r
97--| +-----------------------------------------------+ |\r
98--| | BAR0 (r/w) Base AddRess 0 register | |\r
99--| +-----------------------------------------------+-----------------------+ |\r
100--| | BAR032MBb(6..0) | -- | (31-24) |\r
101--| +-----------------------------------------------------------------------+ |\r
102--| | BAR032MBb : Base Address 32MBytes decode space (7 bits) | |\r
103--| +-----------------------------------------------------------------------+ |\r
104--| |\r
105--| +-----------------------------------------------+ |\r
106--| | SUBSYSTEMVID (r) SUBSYSTEM Vendor ID register | |\r
107--| +-----------------------------------------------+-----------------------+ |\r
108--| | Identifies vendor of add-in board or subsystem. | |\r
109--| | SUBSYSTEMVIDr : subsystemvID (generic) | |\r
110--| +-----------------------------------------------------------------------+ |\r
111--| |\r
112--| +-----------------------------------------------+ |\r
113--| | SUBSYSTEMID (r) SUBSYSTEM ID register | |\r
114--| +-----------------------------------------------+-----------------------+ |\r
115--| | Vendor specific. | |\r
116--| | SUBSYTEMIDr : subsytemID (generic) | |\r
117--| +-----------------------------------------------------------------------+ |\r
118--| |\r
119--| +-----------------------------------------------+ |\r
120--| | INTLINE (r/w) INTerrupt LINE register | |\r
121--| +-----------------------------------------------+-----------------------+ |\r
122--| | INTLINEr(7..0) | (7..0) |\r
123--| +-----------------------------------------------------------------------+ |\r
124--| | Interrupt Line routing information | |\r
125--| +-----------------------------------------------------------------------+ |\r
126--| |\r
127--| +-----------------------------------------------+ |\r
128--| | INTPIN (r) INTerrupt PIN register | |\r
129--| +-----------------------------------------------+-----------------------+ |\r
130--| | Tells which interrupt pin the device uses: 01=INTA | |\r
131--| +-----------------------------------------------------------------------+ |\r
132--| |\r
133--+-------------------------------------------------------------------------------------------------+\r
134--| |\r
135--| Revision history : |\r
136--| Date Version Author Description |\r
137--| 2005-05-13 R00A00 PAU First alfa revision (eng) |\r
138--| |\r
139--| To do: |\r
140--| |\r
141--+-------------------------------------------------------------------------------------------------+\r
142--+-----------------------------------------------------------------+\r
143--| |\r
144--| Copyright (C) 2005 Peio Azkarate, peio@opencores.org | \r
145--| |\r
146--| This source file may be used and distributed without |\r
147--| restriction provided that this copyright statement is not |\r
148--| removed from the file and that any derivative work contains |\r
149--| the original copyright notice and the associated disclaimer. |\r
150--| |\r
151--| This source file is free software; you can redistribute it |\r
152--| and/or modify it under the terms of the GNU Lesser General |\r
153--| Public License as published by the Free Software Foundation; |\r
154--| either version 2.1 of the License, or (at your option) any |\r
155--| later version. |\r
156--| |\r
157--| This source is distributed in the hope that it will be |\r
158--| useful, but WITHOUT ANY WARRANTY; without even the implied |\r
159--| warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR |\r
160--| PURPOSE. See the GNU Lesser General Public License for more |\r
161--| details. |\r
162--| |\r
163--| You should have received a copy of the GNU Lesser General |\r
164--| Public License along with this source; if not, download it |\r
165--| from http://www.opencores.org/lgpl.shtml |\r
166--| |\r
167--+-----------------------------------------------------------------+ \r
168\r
169\r
170--+-----------------------------------------------------------------------------+\r
171--| LIBRARIES |\r
172--+-----------------------------------------------------------------------------+\r
173\r
174library ieee;\r
175use ieee.std_logic_1164.all;\r
176\r
177\r
178--+-----------------------------------------------------------------------------+\r
179--| ENTITY |\r
180--+-----------------------------------------------------------------------------+\r
181\r
182entity pciregs is\r
183generic (\r
184\r
185 vendorID : std_logic_vector(15 downto 0);\r
186 deviceID : std_logic_vector(15 downto 0);\r
187 revisionID : std_logic_vector(7 downto 0);\r
188 subsystemID : std_logic_vector(15 downto 0);\r
189 subsystemvID : std_logic_vector(15 downto 0);\r
190 jcarr1ID : std_logic_vector(31 downto 0);\r
191 jcarr2ID : std_logic_vector(31 downto 0);\r
192 jcarr3ID : std_logic_vector(31 downto 0);\r
193 jcarr4ID : std_logic_vector(31 downto 0);\r
194 jcarr5ID : std_logic_vector(31 downto 0);\r
195 jcarr6ID : std_logic_vector(31 downto 0);\r
196 jcarr7ID : std_logic_vector(31 downto 0);\r
197 jcarr8ID : std_logic_vector(31 downto 0);\r
198 jcarr9ID : std_logic_vector(31 downto 0);\r
199 jcarr10ID : std_logic_vector(31 downto 0);\r
200 jcarr11ID : std_logic_vector(31 downto 0);\r
201 jcarr12ID : std_logic_vector(31 downto 0);\r
202 jcarr13ID : std_logic_vector(31 downto 0);\r
203 jcarr14ID : std_logic_vector(31 downto 0);\r
204 jcarr15ID : std_logic_vector(31 downto 0);\r
205 jcarr16ID : std_logic_vector(31 downto 0);\r
206 jcarr17ID : std_logic_vector(31 downto 0);\r
207 jcarr18ID : std_logic_vector(31 downto 0);\r
208 jcarr19ID : std_logic_vector(31 downto 0);\r
209 jcarr20ID : std_logic_vector(31 downto 0);\r
210 jcarr21ID : std_logic_vector(31 downto 0);\r
211 jcarr22ID : std_logic_vector(31 downto 0);\r
212 jcarr23ID : std_logic_vector(31 downto 0);\r
213 jcarr24ID : std_logic_vector(31 downto 0);\r
214 jcarr25ID : std_logic_vector(31 downto 0);\r
215 jcarr26ID : std_logic_vector(31 downto 0);\r
216 jcarr27ID : std_logic_vector(31 downto 0);\r
217 jcarr28ID : std_logic_vector(31 downto 0);\r
218 jcarr29ID : std_logic_vector(31 downto 0);\r
219 jcarr30ID : std_logic_vector(31 downto 0);\r
220 jcarr31ID : std_logic_vector(31 downto 0);\r
221 jcarr32ID : std_logic_vector(31 downto 0);\r
222 jcarr33ID : std_logic_vector(31 downto 0);\r
223 jcarr34ID : std_logic_vector(31 downto 0);\r
224 jcarr35ID : std_logic_vector(31 downto 0);\r
225 jcarr36ID : std_logic_vector(31 downto 0);\r
226 jcarr37ID : std_logic_vector(31 downto 0);\r
227 jcarr38ID : std_logic_vector(31 downto 0);\r
228 jcarr39ID : std_logic_vector(31 downto 0);\r
229 jcarr40ID : std_logic_vector(31 downto 0);\r
230 jcarr41ID : std_logic_vector(31 downto 0);\r
231 jcarr42ID : std_logic_vector(31 downto 0)\r
232\r
233);\r
234port (\r
235\r
236 -- General \r
237 clk_i : in std_logic;\r
238 nrst_i : in std_logic;\r
239 -- \r
240 adr_i : in std_logic_vector(5 downto 0);\r
241 cbe_i : in std_logic_vector(3 downto 0);\r
242 dat_i : in std_logic_vector(31 downto 0);\r
243 dat_o : out std_logic_vector(31 downto 0);\r
244 --\r
245 wrcfg_i : in std_logic;\r
246 rdcfg_i : in std_logic;\r
247 perr_i : in std_logic;\r
248 serr_i : in std_logic;\r
249 tabort_i : in std_logic;\r
250 --\r
251 bar0_o : out std_logic_vector(31 downto 25);\r
252 perrEN_o : out std_logic;\r
253 serrEN_o : out std_logic;\r
254 memEN_o : out std_logic\r
255 \r
256); \r
257end pciregs;\r
258\r
259\r
260architecture rtl of pciregs is\r
261\r
262\r
263--+-----------------------------------------------------------------------------+\r
264--| COMPONENTS |\r
265--+-----------------------------------------------------------------------------+\r
266--+-----------------------------------------------------------------------------+\r
267--| CONSTANTS |\r
268--+-----------------------------------------------------------------------------+\r
269\r
270 constant CLASSCODEr : std_logic_vector(23 downto 0) := X"028000"; -- Bridge-OtherBridgeDevice\r
271 constant REVISIONIDr : std_logic_vector(7 downto 0) := revisionID; -- PR00=80,PR1=81...\r
272 constant HEADERTYPEr : std_logic_vector(7 downto 0) := X"00"; \r
273 constant DEVSELTIMb : std_logic_vector(1 downto 0) := b"01"; -- DEVSEL TIMing (bits) medium speed\r
274 constant VENDORIDr : std_logic_vector(15 downto 0) := vendorID; \r
275 constant DEVICEIDr : std_logic_vector(15 downto 0) := deviceID; \r
276 constant SUBSYSTEMIDr : std_logic_vector(15 downto 0) := subsystemID; \r
277 constant SUBSYSTEMVIDr : std_logic_vector(15 downto 0) := subsystemvID; \r
278 constant JCARR1IDr : std_logic_vector(31 downto 0) := jcarr1ID;\r
279 constant JCARR2IDr : std_logic_vector(31 downto 0) := jcarr2ID;\r
280 constant JCARR3IDr : std_logic_vector(31 downto 0) := jcarr3ID;\r
281 constant JCARR4IDr : std_logic_vector(31 downto 0) := jcarr4ID;\r
282 constant JCARR5IDr : std_logic_vector(31 downto 0) := jcarr5ID;\r
283 constant JCARR6IDr : std_logic_vector(31 downto 0) := jcarr6ID;\r
284 constant JCARR7IDr : std_logic_vector(31 downto 0) := jcarr7ID;\r
285 constant JCARR8IDr : std_logic_vector(31 downto 0) := jcarr8ID;\r
286 constant JCARR9IDr : std_logic_vector(31 downto 0) := jcarr9ID;\r
287 constant JCARR10IDr : std_logic_vector(31 downto 0) := jcarr10ID;\r
288 constant JCARR11IDr : std_logic_vector(31 downto 0) := jcarr11ID;\r
289 constant JCARR12IDr : std_logic_vector(31 downto 0) := jcarr12ID;\r
290 constant JCARR13IDr : std_logic_vector(31 downto 0) := jcarr13ID;\r
291 constant JCARR14IDr : std_logic_vector(31 downto 0) := jcarr14ID;\r
292 constant JCARR15IDr : std_logic_vector(31 downto 0) := jcarr15ID;\r
293 constant JCARR16IDr : std_logic_vector(31 downto 0) := jcarr16ID;\r
294 constant JCARR17IDr : std_logic_vector(31 downto 0) := jcarr17ID;\r
295 constant JCARR18IDr : std_logic_vector(31 downto 0) := jcarr18ID;\r
296 constant JCARR19IDr : std_logic_vector(31 downto 0) := jcarr19ID;\r
297 constant JCARR20IDr : std_logic_vector(31 downto 0) := jcarr20ID;\r
298 constant JCARR21IDr : std_logic_vector(31 downto 0) := jcarr21ID;\r
299 constant JCARR22IDr : std_logic_vector(31 downto 0) := jcarr22ID;\r
300 constant JCARR23IDr : std_logic_vector(31 downto 0) := jcarr23ID;\r
301 constant JCARR24IDr : std_logic_vector(31 downto 0) := jcarr24ID;\r
302 constant JCARR25IDr : std_logic_vector(31 downto 0) := jcarr25ID;\r
303 constant JCARR26IDr : std_logic_vector(31 downto 0) := jcarr26ID;\r
304 constant JCARR27IDr : std_logic_vector(31 downto 0) := jcarr27ID;\r
305 constant JCARR28IDr : std_logic_vector(31 downto 0) := jcarr28ID;\r
306 constant JCARR29IDr : std_logic_vector(31 downto 0) := jcarr29ID;\r
307 constant JCARR30IDr : std_logic_vector(31 downto 0) := jcarr30ID;\r
308 constant JCARR31IDr : std_logic_vector(31 downto 0) := jcarr31ID;\r
309 constant JCARR32IDr : std_logic_vector(31 downto 0) := jcarr32ID;\r
310 constant JCARR33IDr : std_logic_vector(31 downto 0) := jcarr33ID;\r
311 constant JCARR34IDr : std_logic_vector(31 downto 0) := jcarr34ID;\r
312 constant JCARR35IDr : std_logic_vector(31 downto 0) := jcarr35ID;\r
313 constant JCARR36IDr : std_logic_vector(31 downto 0) := jcarr36ID;\r
314 constant JCARR37IDr : std_logic_vector(31 downto 0) := jcarr37ID;\r
315 constant JCARR38IDr : std_logic_vector(31 downto 0) := jcarr38ID;\r
316 constant JCARR39IDr : std_logic_vector(31 downto 0) := jcarr39ID;\r
317 constant JCARR40IDr : std_logic_vector(31 downto 0) := jcarr40ID;\r
318 constant JCARR41IDr : std_logic_vector(31 downto 0) := jcarr41ID;\r
319 constant JCARR42IDr : std_logic_vector(31 downto 0) := jcarr42ID;\r
320 constant INTPINr : std_logic_vector(7 downto 0) := X"01"; -- INTA#\r
321\r
322\r
323--+-----------------------------------------------------------------------------+\r
324--| SIGNALS |\r
325--+-----------------------------------------------------------------------------+\r
326\r
327 signal dataout : std_logic_vector(31 downto 0);\r
328 signal tabortPFS : std_logic;\r
329 signal serrPFS : std_logic;\r
330 signal perrPFS : std_logic;\r
331 signal adrSTCMD : std_logic;\r
332 signal adrBAR0 : std_logic;\r
333 signal adrINT : std_logic;\r
334 signal we0CMD : std_logic;\r
335 signal we1CMD : std_logic;\r
336 signal we3ST : std_logic;\r
337 signal we3BAR0 : std_logic;\r
338 signal we0INT : std_logic;\r
339 signal we1INT : std_logic;\r
340 signal st11SEN : std_logic;\r
341 signal st11REN : std_logic;\r
342 signal st14SEN : std_logic;\r
343 signal st14REN : std_logic;\r
344 signal st15SEN : std_logic;\r
345 signal st15REN : std_logic;\r
346\r
347\r
348 --+---------------------------------------------------------+\r
349 --| CONFIGURATION SPACE REGISTERS |\r
350 --+---------------------------------------------------------+\r
351\r
352 -- INTERRUPT LINE register \r
353 signal INTLINEr : std_logic_vector(7 downto 0);\r
354 -- COMMAND register bits\r
355 signal MEMSPACEENb : std_logic; -- Memory SPACE ENable (bit)\r
356 signal PERRENb : std_logic; -- Parity ERRor ENable (bit)\r
357 signal SERRENb : std_logic; -- SERR ENable (bit)\r
358 -- STATUS register bits\r
359 --signal DEVSELTIMb : std_logic_vector(1 downto 0); -- DEVSEL TIMing (bits)\r
360 signal TABORTSIb : std_logic; -- TarGet ABORT SIgnaling (bit)\r
361 signal SERRSIb : std_logic; -- System ERRor SIgnaling (bit)\r
362 signal PERRDTb : std_logic; -- Parity ERRor DeTected (bit)\r
363 -- BAR0 register bits\r
364 signal BAR032MBb : std_logic_vector(6 downto 0); -- BAR0 32MBytes Space (bits)\r
365 \r
366\r
367component pfs\r
368port (\r
369 clk : in std_logic;\r
370 a : in std_logic;\r
371 y : out std_logic\r
372); \r
373\r
374end component;\r
375\r
376begin\r
377\r
378 --+-------------------------------------------------------------------------+\r
379 --| Component instances |\r
380 --+-------------------------------------------------------------------------+\r
381\r
382 u1: pfs port map ( clk => clk_i, a => tabort_i, y => tabortPFS );\r
383 u2: pfs port map ( clk => clk_i, a => serr_i, y => serrPFS );\r
384 u3: pfs port map ( clk => clk_i, a => perr_i, y => perrPFS );\r
385 \r
386\r
387 --+-------------------------------------------------------------------------+\r
388 --| Registers Address Decoder |\r
389 --+-------------------------------------------------------------------------+\r
390\r
391 adrSTCMD <= '1' when ( adr_i(5 downto 0) = b"000001" ) else '0';\r
392 adrBAR0 <= '1' when ( adr_i(5 downto 0) = b"000100" ) else '0';\r
393 adrINT <= '1' when ( adr_i(5 downto 0) = b"001111" ) else '0';\r
394\r
395\r
396 --+-------------------------------------------------------------------------+\r
397 --| WRITE ENABLE REGISTERS |\r
398 --+-------------------------------------------------------------------------+\r
399\r
400 --+-----------------------------------------+\r
401 --| Write Enable Registers |\r
402 --+-----------------------------------------+\r
403 \r
404 we0CMD <= adrSTCMD and wrcfg_i and (not cbe_i(0));\r
405 we1CMD <= adrSTCMD and wrcfg_i and (not cbe_i(1));\r
406 --we2ST <= adrSTCMD and wrcfg_i and (not cbe_i(2));\r
407 we3ST <= adrSTCMD and wrcfg_i and (not cbe_i(3));\r
408 --we2BAR0 <= adrBAR0 and wrcfg_i and (not cbe_i(2));\r
409 we3BAR0 <= adrBAR0 and wrcfg_i and (not cbe_i(3));\r
410 we0INT <= adrINT and wrcfg_i and (not cbe_i(0));\r
411 --we1INT <= adrINT and wrcfg_i and (not cbe_i(1));\r
412\r
413 --+-----------------------------------------+\r
414 --| Set Enable & Reset Enable bits |\r
415 --+-----------------------------------------+\r
416 st11SEN <= tabortPFS; \r
417 st11REN <= we3ST and dat_i(27);\r
418 st14SEN <= serrPFS; \r
419 st14REN <= we3ST and dat_i(30);\r
420 st15SEN <= perrPFS; \r
421 st15REN <= we3ST and dat_i(31);\r
422\r
423\r
424 --+-------------------------------------------------------------------------+\r
425 --| WRITE REGISTERS |\r
426 --+-------------------------------------------------------------------------+\r
427\r
428 --+---------------------------------------------------------+\r
429 --| COMMAND REGISTER Write |\r
430 --+---------------------------------------------------------+\r
431\r
432 REGCMDWR: process( clk_i, nrst_i, we0CMD, we1CMD, dat_i )\r
433 begin\r
434\r
435 if( nrst_i = '0' ) then\r
436 MEMSPACEENb <= '0';\r
437 PERRENb <= '0';\r
438 SERRENb <= '0'; \r
439 elsif( rising_edge( clk_i ) ) then\r
440\r
441 -- Byte 0\r
442 if( we0CMD = '1' ) then\r
443 MEMSPACEENb <= dat_i(1);\r
444 PERRENb <= dat_i(6); \r
445 end if;\r
446 \r
447 -- Byte 1\r
448 if( we1CMD = '1' ) then\r
449 SERRENb <= dat_i(8); \r
450 end if;\r
451\r
452 end if;\r
453\r
454 end process REGCMDWR;\r
455\r
456\r
457 --+---------------------------------------------------------+\r
458 --| STATUS REGISTER WRITE (Reset only) |\r
459 --+---------------------------------------------------------+\r
460\r
461 REGSTWR: process( clk_i, nrst_i, st11SEN, st11REN, st14SEN, st14REN, st15SEN, st15REN )\r
462 begin\r
463\r
464 if( nrst_i = '0' ) then\r
465 TABORTSIb <= '0';\r
466 SERRSIb <= '0';\r
467 PERRDTb <= '0';\r
468 elsif( rising_edge( clk_i ) ) then\r
469\r
470 -- TarGet ABORT SIgnaling bit\r
471 if( st11SEN = '1' ) then\r
472 TABORTSIb <= '1';\r
473 elsif ( st11REN = '1' ) then\r
474 TABORTSIb <= '0'; \r
475 end if;\r
476\r
477 -- System ERRor SIgnaling bit\r
478 if( st14SEN = '1' ) then\r
479 SERRSIb <= '1';\r
480 elsif ( st14REN = '1' ) then\r
481 SERRSIb <= '0'; \r
482 end if;\r
483\r
484 -- Parity ERRor DEtected bit\r
485 if( st15SEN = '1' ) then\r
486 PERRDTb <= '1';\r
487 elsif ( st15REN = '1' ) then\r
488 PERRDTb <= '0'; \r
489 end if;\r
490 \r
491 end if;\r
492\r
493 end process REGSTWR;\r
494\r
495\r
496 --+---------------------------------------------------------+\r
497 --| INTERRUPT REGISTER Write |\r
498 --+---------------------------------------------------------+\r
499\r
500 REGINTWR: process( clk_i, nrst_i, we0INT, dat_i )\r
501 begin\r
502\r
503 if( nrst_i = '0' ) then\r
504 INTLINEr <= ( others => '0' );\r
505 elsif( rising_edge( clk_i ) ) then\r
506\r
507 -- Byte 0\r
508 if( we0INT = '1' ) then\r
509 INTLINEr <= dat_i(7 downto 0);\r
510 end if;\r
511 \r
512\r
513 end if;\r
514\r
515 end process REGINTWR;\r
516\r
517\r
518 --+---------------------------------------------------------+\r
519 --| BAR0 32MBytes address space (bits 31-25) |\r
520 --+---------------------------------------------------------+\r
521\r
522 REGBAR0WR: process( clk_i, nrst_i, we3BAR0, dat_i )\r
523 begin\r
524\r
525 if( nrst_i = '0' ) then\r
526 BAR032MBb <= ( others => '1' );\r
527 elsif( rising_edge( clk_i ) ) then\r
528\r
529 -- Byte 3\r
530 if( we3BAR0 = '1' ) then\r
531 BAR032MBb <= dat_i(31 downto 25);\r
532 end if;\r
533 \r
534 end if;\r
535\r
536 end process REGBAR0WR;\r
537\r
538\r
539 --+-------------------------------------------------------------------------+\r
540 --| Registers MUX (READ) |\r
541 --+-------------------------------------------------------------------------+\r
542--+-------------------------------------------------------------------------------------------------+\r
543\r
544 RRMUX: process( adr_i, PERRDTb, SERRSIb, TABORTSIb, SERRENb, PERRENb, MEMSPACEENb, BAR032MBb, \r
545 INTLINEr, rdcfg_i )\r
546 begin\r
547\r
548 if ( rdcfg_i = '1' ) then\r
549 \r
550 case adr_i is\r
551\r
552 when b"000000" => \r
553 dataout <= DEVICEIDr & VENDORIDr;\r
554 when b"000001" => \r
555 dataout <= PERRDTb & SERRSIb & b"00" & TABORTSIb & DEVSELTIMb & b"000000000" &\r
556 b"0000000" & SERRENb & b"0" & PERRENb & b"0000" & MEMSPACEENb & b"0";\r
557 when b"000010" => \r
558 dataout <= CLASSCODEr & REVISIONIDr;\r
559 when b"000100" => \r
560 dataout <= BAR032MBb & b"0" & b"00000000" & b"00000000" & b"00000000";\r
561 when b"001011" => \r
562 dataout <= SUBSYSTEMIDr & SUBSYSTEMVIDr;\r
563 when b"001111" => \r
564 dataout <= b"0000000000000000" & INTPINr & INTLINEr;\r
565 when b"010001" =>\r
566 dataout <= JCARR1IDr;\r
567 when b"010010" =>\r
568 dataout <= JCARR2IDr;\r
569 when b"010011" =>\r
570 dataout <= JCARR3IDr;\r
571 when b"010100" =>\r
572 dataout <= JCARR4IDr;\r
573 when b"010101" =>\r
574 dataout <= JCARR5IDr;\r
575 when b"010110" =>\r
576 dataout <= JCARR6IDr;\r
577 when b"010111" =>\r
578 dataout <= JCARR7IDr;\r
579 when b"011000" =>\r
580 dataout <= JCARR8IDr;\r
581 when b"011001" =>\r
582 dataout <= JCARR9IDr;\r
583 when b"011010" =>\r
584 dataout <= JCARR10IDr;\r
585 when b"011011" =>\r
586 dataout <= JCARR11IDr;\r
587 when b"011100" =>\r
588 dataout <= JCARR12IDr;\r
589 when b"011101" =>\r
590 dataout <= JCARR13IDr;\r
591 when b"011110" =>\r
592 dataout <= JCARR14IDr;\r
593 when b"011111" =>\r
594 dataout <= JCARR15IDr;\r
595 when b"100000" =>\r
596 dataout <= JCARR16IDr;\r
597 when b"100001" =>\r
598 dataout <= JCARR17IDr;\r
599 when b"100010" =>\r
600 dataout <= JCARR18IDr;\r
601 when b"100011" =>\r
602 dataout <= JCARR19IDr;\r
603 when b"100100" =>\r
604 dataout <= JCARR20IDr;\r
605 when b"100101" =>\r
606 dataout <= JCARR21IDr;\r
607 when b"100110" =>\r
608 dataout <= JCARR22IDr;\r
609 when b"100111" =>\r
610 dataout <= JCARR23IDr;\r
611 when b"101000" =>\r
612 dataout <= JCARR24IDr;\r
613 when b"101001" =>\r
614 dataout <= JCARR25IDr;\r
615 when b"101010" =>\r
616 dataout <= JCARR26IDr;\r
617 when b"101011" =>\r
618 dataout <= JCARR27IDr;\r
619 when b"101100" =>\r
620 dataout <= JCARR28IDr;\r
621 when b"101101" =>\r
622 dataout <= JCARR29IDr;\r
623 when b"101110" =>\r
624 dataout <= JCARR30IDr;\r
625 when b"101111" =>\r
626 dataout <= JCARR31IDr;\r
627 when b"110000" =>\r
628 dataout <= JCARR32IDr;\r
629 when b"110001" =>\r
630 dataout <= JCARR33IDr;\r
631 when b"110010" =>\r
632 dataout <= JCARR34IDr;\r
633 when b"110011" =>\r
634 dataout <= JCARR35IDr;\r
635 when b"110100" =>\r
636 dataout <= JCARR36IDr;\r
637 when b"110101" =>\r
638 dataout <= JCARR37IDr;\r
639 when b"110110" =>\r
640 dataout <= JCARR38IDr;\r
641 when b"110111" =>\r
642 dataout <= JCARR39IDr;\r
643 when b"111000" =>\r
644 dataout <= JCARR40IDr;\r
645 when b"111001" =>\r
646 dataout <= JCARR41IDr;\r
647 when b"111010" =>\r
648 dataout <= JCARR42IDr;\r
649 when others => \r
650 dataout <= ( others => '0' );\r
651\r
652 end case;\r
653 \r
654 else\r
655 \r
656 dataout <= ( others => '0' );\r
657 \r
658 end if;\r
659\r
660 end process RRMUX;\r
661\r
662 dat_o <= dataout;\r
663 \r
664 \r
665 --+-------------------------------------------------------------------------+\r
666 --| BAR0 & COMMAND REGS bits outputs |\r
667 --+-------------------------------------------------------------------------+\r
668 \r
669 bar0_o <= BAR032MBb;\r
670 perrEN_o <= PERRENb;\r
671 serrEN_o <= SERRENb; \r
672 memEN_o <= MEMSPACEENb;\r
673\r
674 \r
675end rtl;\r
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