chipscope

[raggedstone] / dhwk / source / config_3Ch.vhd

-- J.STELZNER\r
-- INFORMATIK-3 LABOR\r
-- 23.08.2006\r
-- File: CONFIG_3CH.VHD\r
\r
library IEEE;\r
use IEEE.std_logic_1164.all;\r
\r
entity CONFIG_3CH is\r
    port\r
	(\r
	PCI_CLOCK			:in		std_logic;\r
	PCI_RSTn			:in		std_logic;\r
	AD_REG				:in		std_logic_vector (31 downto 0);\r
	CBE_REGn			:in		std_logic_vector ( 3 downto 0);\r
	CONF_WR_3CH	 	:in		std_logic;\r
	CONF_DATA_3CH	:out	std_logic_vector (31 downto 0)\r
    );\r
end entity CONFIG_3CH;\r
\r
architecture CONFIG_3CH_DESIGN of CONFIG_3CH is\r
\r
-- PCI Configuration Space Header Addr : HEX 3C --\r
\r
	signal		CONF_MAX_LAT		:std_logic_vector (31 downto 24);\r
	signal		CONF_MIN_GNT		:std_logic_vector (23 downto 16);  \r
	signal		CONF_INT_PIN		:std_logic_vector (15 downto  8);\r
	signal		CONF_INT_LINE		:std_logic_vector ( 7 downto  0);  \r
\r
begin \r
\r
--*******************************************************************\r
--*********** PCI Configuration Space Header "INTERRUPT" ************\r
--*******************************************************************\r
\r
		CONF_MAX_LAT	<= X"00";\r
		CONF_MIN_GNT	<= X"00";\r
--	CONF_INT_PIN	<= X"00";				-- Interrupt -\r
		CONF_INT_PIN	<= X"01";				-- Interrupt A\r
--	CONF_INT_PIN	<= X"02";				-- Interrupt B\r
--	CONF_INT_PIN	<= X"03";				-- Interrupt C \r
--	CONF_INT_PIN	<= X"04";				-- Interrupt D\r
--	CONF_INT_PIN	<= X"05 - FF0";	-- Reserviert\r
\r
	process (PCI_CLOCK,PCI_RSTn) \r
	begin\r
		if PCI_RSTn = '0' then	CONF_INT_LINE <= (others =>'0');\r
	\r
		elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
\r
			if			CONF_WR_3CH	 = '1'and CBE_REGn(0) = '0' then \r
\r
							CONF_INT_LINE(7 downto 0) <= AD_REG(7 downto 0);\r
				else 	CONF_INT_LINE(7 downto 0) <= CONF_INT_LINE(7 downto 0);\r
			end if;\r
\r
		end if;\r
\r
	end process;\r
\r
	CONF_DATA_3CH	<= CONF_MAX_LAT & CONF_MIN_GNT & CONF_INT_PIN & CONF_INT_LINE ;\r
\r
end architecture CONFIG_3CH_DESIGN;\r
\r
\r
\r