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377c0242 1-- VHDL model created from schematic reg_io.sch -- Jan 09 09:34:12 2007\r
2\r
3\r
4\r
5LIBRARY ieee;\r
6\r
7USE ieee.std_logic_1164.ALL;\r
8USE ieee.numeric_std.ALL;\r
9\r
10\r
11entity REG_IO is\r
12 Port ( AD_REG : In std_logic_vector (31 downto 0);\r
13 PCI_CLOCK : In std_logic;\r
14 RESET : In std_logic;\r
15 WRITE_XX1_0 : In std_logic;\r
16 WRITE_XX7_6 : In std_logic;\r
17 REG_OUT_XX0 : Out std_logic_vector (7 downto 0);\r
18 REG_OUT_XX6 : Out std_logic_vector (7 downto 0);\r
19 REG_OUT_XX7 : Out std_logic_vector (7 downto 0) );\r
20end REG_IO;\r
21\r
22architecture SCHEMATIC of REG_IO is\r
23\r
24 SIGNAL gnd : std_logic := '0';\r
25 SIGNAL vcc : std_logic := '1';\r
26\r
27\r
28 component REG\r
29 Port ( CLOCK : In std_logic;\r
30 REG_IN : In std_logic_vector (7 downto 0);\r
31 RESET : In std_logic;\r
32 WRITE : In std_logic;\r
33 REG_OUT : Out std_logic_vector (7 downto 0) );\r
34 end component;\r
35\r
36begin\r
37\r
38 I14 : REG\r
39 Port Map ( CLOCK=>PCI_CLOCK,\r
40 REG_IN(7 downto 0)=>AD_REG(7 downto 0), RESET=>RESET,\r
41 WRITE=>WRITE_XX1_0,\r
42 REG_OUT(7 downto 0)=>REG_OUT_XX0(7 downto 0) );\r
43 I15 : REG\r
44 Port Map ( CLOCK=>PCI_CLOCK,\r
45 REG_IN(7 downto 0)=>AD_REG(31 downto 24), RESET=>RESET,\r
46 WRITE=>WRITE_XX7_6,\r
47 REG_OUT(7 downto 0)=>REG_OUT_XX7(7 downto 0) );\r
48 I16 : REG\r
49 Port Map ( CLOCK=>PCI_CLOCK,\r
50 REG_IN(7 downto 0)=>AD_REG(23 downto 16), RESET=>RESET,\r
51 WRITE=>WRITE_XX7_6,\r
52 REG_OUT(7 downto 0)=>REG_OUT_XX6(7 downto 0) );\r
53\r
54end SCHEMATIC;\r
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