level

[raggedstone] / dhwk / source / Io_reg.vhd

-- J.STELZNER\r
-- INFORMATIK-3 LABOR\r
-- 23.08.2006\r
-- File: IO_MUX.VHD\r
\r
library ieee;\r
use ieee.std_logic_1164.all;\r
\r
entity IO_REG is\r
    port\r
	(\r
	PCI_CLOCK		:in		std_logic;\r
	PCI_RSTn		:in		std_logic;\r
	PCI_FRAMEn	:in		std_logic;\r
	PCI_IRDYn		:in		std_logic;\r
	PCI_IDSEL		:in		std_logic;\r
	PCI_PAR			:in		std_logic;\r
	PCI_CBEn		:in		std_logic_vector ( 3 downto 0);\r
	OE_PCI_AD		:in		std_logic;\r
	IO_DATA			:in		std_logic_vector (31 downto 0);\r
	AD_REG			:out	std_logic_vector (31 downto 0);\r
	CBE_REGn		:out	std_logic_vector ( 3 downto 0);\r
	FRAME_REGn	:out	std_logic;	\r
	IRDY_REGn		:out	std_logic;	\r
	IDSEL_REG		:out	std_logic;\r
	PAR_REG			:out	std_logic;		\r
	PCI_AD			:out	std_logic_vector (31 downto 0)	--	t/s\r
    );\r
end entity IO_REG;\r
\r
architecture IO_REG_DESIGN of IO_REG is\r
\r
	signal	REG_AD			:std_logic_vector (31 downto 0); \r
	signal	REG_CBEn		:std_logic_vector ( 3 downto 0);\r
	signal	REG_FRAMEn	:std_logic;\r
	signal	REG_IRDYn		:std_logic;\r
	signal	REG_IDSEL		:std_logic;\r
	signal	REG_PAR			:std_logic;\r
\r
begin \r
\r
	process (PCI_CLOCK, PCI_RSTn) \r
	begin\r
		if	PCI_RSTn = '0'	then\r
\r
			REG_AD			<= X"00000000";\r
			REG_CBEn		<= "0000";\r
			REG_FRAMEn	<= '1';\r
			REG_IRDYn		<= '1';\r
			REG_IDSEL		<= '0';\r
			REG_PAR			<= '0';\r
\r
		elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
\r
			REG_AD			<=	IO_DATA;\r
			REG_CBEn		<=	PCI_CBEn;\r
		 	REG_FRAMEn	<=	PCI_FRAMEn;\r
			REG_IRDYn		<=	PCI_IRDYn;\r
			REG_IDSEL		<=	PCI_IDSEL;\r
			REG_PAR			<=	PCI_PAR;\r
\r
		end if;\r
	end process;\r
\r
	PCI_AD			<=	REG_AD when OE_PCI_AD ='1' else (others => 'Z');\r
\r
	AD_REG			<=	REG_AD;\r
	CBE_REGn		<=	REG_CBEn;\r
 	FRAME_REGn	<=	REG_FRAMEn;\r
	IRDY_REGn		<=	REG_IRDYn;\r
	IDSEL_REG		<=	REG_IDSEL;\r
	PAR_REG			<=	REG_PAR;\r
\r
end architecture IO_REG_DESIGN;\r