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[raggedstone] / dhwk / source / FLAG_BUS.vhd
CommitLineData
696ded12 1-- J.STELZNER
2-- INFORMATIK-3 LABOR
3-- 23.08.2006
4-- File: FLAG_BUS.VHD
5
6library IEEE;
7use IEEE.std_logic_1164.all;
8
9entity FLAG_BUS is
2612d712 10 port
11 (
12 PCI_CLOCK :in std_logic;
13 KONS_1 :in std_logic;
14 FLAG_IN_0 :in std_logic;
15 R_EFn :in std_logic;
16 R_HFn :in std_logic;
17 R_FFn :in std_logic;
18 FLAG_IN_4 :in std_logic;
19 S_EFn :in std_logic;
20 S_HFn :in std_logic;
21 S_FFn :in std_logic;
22 HOLD :in std_logic;
23 SYNC_FLAG :out std_logic_vector (7 downto 0)
24 );
696ded12 25end entity FLAG_BUS;
26
27architecture FLAG_BUS_DESIGN of FLAG_BUS is
28
29
2612d712 30 signal FF1_S_EFn :std_logic;
31 signal FF1_S_HFn :std_logic;
32 signal FF1_S_FFn :std_logic;
33 signal FF1_R_EFn :std_logic;
34 signal FF1_R_HFn :std_logic;
35 signal FF1_R_FFn :std_logic;
696ded12 36
2612d712 37 signal FF2_S_EFn :std_logic;
38 signal FF2_S_HFn :std_logic;
39 signal FF2_S_FFn :std_logic;
40 signal FF2_R_EFn :std_logic;
41 signal FF2_R_HFn :std_logic;
42 signal FF2_R_FFn :std_logic;
696ded12 43
44begin
45
46
2612d712 47 process (PCI_CLOCK)
48 begin
49 if (PCI_CLOCK'event and PCI_CLOCK = '1') then
50 FF1_S_EFn <= not S_EFn;
51 FF1_S_HFn <= not S_HFn;
52 FF1_S_FFn <= not S_FFn;
53 FF1_R_EFn <= not R_EFn;
54 FF1_R_HFn <= not R_HFn;
55 FF1_R_FFn <= not R_FFn;
56 end if;
57 end process;
58
59
60 process (PCI_CLOCK)
61 begin
62 if (PCI_CLOCK'event and PCI_CLOCK = '1') then
63 if HOLD = '0' then
64 FF2_S_EFn <= FF1_S_EFn;
65 FF2_S_HFn <= FF1_S_HFn;
66 FF2_S_FFn <= FF1_S_FFn;
67 FF2_R_EFn <= FF1_R_EFn;
68 FF2_R_HFn <= FF1_R_HFn;
69 FF2_R_FFn <= FF1_R_FFn;
70
71 elsif HOLD = '1' then
72 FF2_S_EFn <= FF2_S_EFn;
73 FF2_S_HFn <= FF2_S_HFn;
74 FF2_S_FFn <= FF2_S_FFn;
75 FF2_R_EFn <= FF2_R_EFn;
76 FF2_R_HFn <= FF2_R_HFn;
77 FF2_R_FFn <= FF2_R_FFn;
78 end if;
79 end if;
80 end process;
81
82SYNC_FLAG(0) <= FLAG_IN_0;
83SYNC_FLAG(1) <= FF2_R_EFn;
84SYNC_FLAG(2) <= FF2_R_HFn;
85SYNC_FLAG(3) <= FF2_R_FFn;
86SYNC_FLAG(4) <= FLAG_IN_4;
87SYNC_FLAG(5) <= FF2_S_EFn;
88SYNC_FLAG(6) <= FF2_S_HFn;
89SYNC_FLAG(7) <= FF2_S_FFn;
696ded12 90
91end architecture FLAG_BUS_DESIGN;
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