identing
[raggedstone] / dhwk / source / IO_RW_SEL.vhd
CommitLineData
696ded12 1-- J.STELZNER
2-- INFORMATIK-3 LABOR
3-- 23.08.2006
4-- File: CONFIG_WR_SEL.VHD
5
6library IEEE;
7use IEEE.std_logic_1164.all;
8
9entity IO_WR_SEL is
2612d712 10 port
11 (
12 IO_WR_COM :in std_logic;
13 IRDY_REGn :in std_logic;
14 TRDYn :in std_logic;
15 ADDR_REG :in std_logic_vector(31 downto 0);
16 CBE_REGn :in std_logic_vector( 3 downto 0);
17 WRITE_XX1_0 :out std_logic;
18 WRITE_XX3_2 :out std_logic;
19 WRITE_XX5_4 :out std_logic;
20 WRITE_XX7_6 :out std_logic
21 );
696ded12 22end entity IO_WR_SEL;
23
2612d712 24--PCI Byte Enable
25--C/BE[3..0] gueltige Datenbits
696ded12 26-------------------------------
2612d712 27-- 0000 AD 31..0
28-- 1000 AD 23..0
29-- 1100 AD 15..0
30-- 1110 AD 7..0
31-- 0011 AD 31..16
696ded12 32
33architecture IO_WR_SEL_DESIGN of IO_WR_SEL is
34
2612d712 35 signal WR_ENA :std_logic;
36 signal ADDR :std_logic_vector( 5 downto 0);
696ded12 37
38begin
39
2612d712 40 WR_ENA <= '1' when
41 IO_WR_COM = '1' and
42 IRDY_REGn = '0' and
43 TRDYn = '0' else '0';
696ded12 44
2612d712 45 ADDR <= ADDR_REG(3) & ADDR_REG(2) & CBE_REGn;
696ded12 46
2612d712 47 WRITE_XX1_0 <= '1' when WR_ENA = '1' and ADDR = "001100" else '0';
48 WRITE_XX3_2 <= '1' when WR_ENA = '1' and ADDR = "000011" else '0';
49 WRITE_XX5_4 <= '1' when WR_ENA = '1' and ADDR = "011100" else '0';
50 WRITE_XX7_6 <= '1' when WR_ENA = '1' and ADDR = "010011" else '0';
696ded12 51
696ded12 52end architecture IO_WR_SEL_DESIGN;
Impressum, Datenschutz