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[raggedstone] / dhwk / source / Verg_2.vhd
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696ded12 1-- J.STELZNER
2-- INFORMATIK-3 LABOR
3-- 23.08.2006
4-- File: VERG_2.VHD
5
2612d712 6library ieee;
7use ieee.std_logic_1164.all;
8
9entity VERG_2 is
10 port
11 (
12 IN_A :in std_logic_vector(1 downto 0);
13 IN_B :in std_logic_vector(1 downto 0);
14 GLEICH :out std_logic
15 );
16end entity VERG_2;
696ded12 17
18architecture VERG_2_DESIGN of VERG_2 is
19
20begin
21
2612d712 22 process (IN_A,IN_B)
23 begin
696ded12 24
2612d712 25 if IN_A = IN_B then
26 GLEICH <= '1';
27 else
28 GLEICH <= '0';
29 end if;
696ded12 30
2612d712 31end process;
696ded12 32
2612d712 33end architecture VERG_2_DESIGN;
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