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[raggedstone] / dhwk / source / steuerung.vhd
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696ded12 1-- VHDL model created from schematic steuerung.sch -- Jan 09 09:34:14 2007
2
696ded12 3LIBRARY ieee;
696ded12 4USE ieee.std_logic_1164.ALL;
5USE ieee.numeric_std.ALL;
696ded12 6
7entity STEUERUNG is
2612d712 8 Port ( AD_REG : In std_logic_vector (31 downto 0);
9 CBE_REGn : In std_logic_vector (3 downto 0);
10 FRAME_REGn : In std_logic;
11 IDSEL_REG : In std_logic;
12 IO_SPACE : In std_logic;
13 MY_ADDR : In std_logic;
14 PCI_CLOCK : In std_logic;
15 PCI_RSTn : In std_logic;
16 READ_FIFO : In std_logic;
17 CF_RD_COM : Out std_logic;
18 CF_WR_COM : Out std_logic;
19 DEVSELn : Out std_logic;
20 FIFO_RDn : Out std_logic;
21 IO_RD_COM : Out std_logic;
22 IO_WR_COM : Out std_logic;
23 LAR : Out std_logic;
24 OE_PCI_PAR : Out std_logic;
25 OE_PCI_PERR : Out std_logic;
26 PCI_DEVSELn : Out std_logic;
27 PCI_STOPn : Out std_logic;
28 PCI_TRDYn : Out std_logic;
29 PERR_CHECK : Out std_logic;
696ded12 30 READ : Out std_logic;
2612d712 31 SERR_CHECK : Out std_logic;
32 TRDYn : Out std_logic );
696ded12 33end STEUERUNG;
34
35architecture SCHEMATIC of STEUERUNG is
36
2612d712 37 SIGNAL gnd : std_logic := '0';
38 SIGNAL vcc : std_logic := '1';
696ded12 39
2612d712 40 signal DEVSELn_DUMMY : std_logic;
41 signal IO_READ : std_logic;
42 signal IO_WRITE : std_logic;
43 signal CONF_READ : std_logic;
44 signal CONF_WRITE : std_logic;
696ded12 45
2612d712 46 component CONT_FSM
47 Port ( CONF_READ : In std_logic;
48 CONF_WRITE : In std_logic;
49 FIFO_READ : In std_logic;
50 IO_READ : In std_logic;
51 IO_WRITE : In std_logic;
52 PCI_CLOCK : In std_logic;
53 PCI_RSTn : In std_logic;
54 DEVSELn : Out std_logic;
55 FIFO_RDn : Out std_logic;
56 OE_PCI_PAR : Out std_logic;
57 OE_PCI_PERR : Out std_logic;
58 PCI_DEVSELn : Out std_logic;
59 PCI_STOPn : Out std_logic;
60 PCI_TRDYn : Out std_logic;
61 PERR_CHECK : Out std_logic;
62 READ : Out std_logic;
63 TRDYn : Out std_logic );
64 end component;
696ded12 65
2612d712 66 component COMM_FSM
67 Port ( CONF_READ : In std_logic;
68 CONF_WRITE : In std_logic;
69 DEVSELn : In std_logic;
70 IO_READ : In std_logic;
71 IO_WRITE : In std_logic;
72 PCI_CLOCK : In std_logic;
73 PCI_RSTn : In std_logic;
74 CF_RD_COM : Out std_logic;
75 CF_WR_COM : Out std_logic;
76 IO_RD_COM : Out std_logic;
77 IO_WR_COM : Out std_logic );
78 end component;
696ded12 79
2612d712 80 component COMM_DEC
81 Port ( AD_REG : In std_logic_vector (31 downto 0);
82 CBE_REGn : In std_logic_vector (3 downto 0);
83 FRAME_REGn : In std_logic;
84 IDSEL_REG : In std_logic;
85 IO_SPACE : In std_logic;
86 MY_ADDR : In std_logic;
87 PCI_CLOCK : In std_logic;
88 PCI_RSTn : In std_logic;
89 CONF_READ : Out std_logic;
90 CONF_WRITE : Out std_logic;
91 IO_READ : Out std_logic;
92 IO_WRITE : Out std_logic;
93 LAR : Out std_logic;
94 SERR_CHECK : Out std_logic );
95 end component;
696ded12 96
97begin
98
2612d712 99 DEVSELn <= DEVSELn_DUMMY;
696ded12 100
2612d712 101 I1 : CONT_FSM
102 Port Map ( CONF_READ=>CONF_READ, CONF_WRITE=>CONF_WRITE,
103 FIFO_READ=>READ_FIFO, IO_READ=>IO_READ,
104 IO_WRITE=>IO_WRITE, PCI_CLOCK=>PCI_CLOCK,
105 PCI_RSTn=>PCI_RSTn, DEVSELn=>DEVSELn_DUMMY,
106 FIFO_RDn=>FIFO_RDn, OE_PCI_PAR=>OE_PCI_PAR,
107 OE_PCI_PERR=>OE_PCI_PERR, PCI_DEVSELn=>PCI_DEVSELn,
108 PCI_STOPn=>PCI_STOPn, PCI_TRDYn=>PCI_TRDYn,
109 PERR_CHECK=>PERR_CHECK, READ=>READ, TRDYn=>TRDYn );
110 I2 : COMM_FSM
111 Port Map ( CONF_READ=>CONF_READ, CONF_WRITE=>CONF_WRITE,
112 DEVSELn=>DEVSELn_DUMMY, IO_READ=>IO_READ,
113 IO_WRITE=>IO_WRITE, PCI_CLOCK=>PCI_CLOCK,
114 PCI_RSTn=>PCI_RSTn, CF_RD_COM=>CF_RD_COM,
115 CF_WR_COM=>CF_WR_COM, IO_RD_COM=>IO_RD_COM,
116 IO_WR_COM=>IO_WR_COM );
117 I3 : COMM_DEC
118 Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),
119 CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
120 FRAME_REGn=>FRAME_REGn, IDSEL_REG=>IDSEL_REG,
121 IO_SPACE=>IO_SPACE, MY_ADDR=>MY_ADDR,
122 PCI_CLOCK=>PCI_CLOCK, PCI_RSTn=>PCI_RSTn,
123 CONF_READ=>CONF_READ, CONF_WRITE=>CONF_WRITE,
124 IO_READ=>IO_READ, IO_WRITE=>IO_WRITE, LAR=>LAR,
125 SERR_CHECK=>SERR_CHECK );
696ded12 126
127end SCHEMATIC;
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