fifo
[raggedstone] / dhwk / source / top.vhd
CommitLineData
377c0242 1-- VHDL model created from schematic top.sch -- Jan 09 20:54:18 2007\r
2\r
3\r
4\r
5LIBRARY ieee;\r
6\r
7USE ieee.std_logic_1164.ALL;\r
8USE ieee.numeric_std.ALL;\r
9\r
10\r
62946980 11entity dhwk is\r
377c0242 12 Port ( KONST_1 : In std_logic;\r
13 PCI_CBEn : In std_logic_vector (3 downto 0);\r
14 PCI_CLOCK : In std_logic;\r
15 PCI_FRAMEn : In std_logic;\r
16 PCI_IDSEL : In std_logic;\r
17 PCI_IRDYn : In std_logic;\r
18 PCI_RSTn : In std_logic;\r
377c0242 19 SERIAL_IN : In std_logic;\r
20 SPC_RDY_IN : In std_logic;\r
21 TAST_RESn : In std_logic;\r
22 TAST_SETn : In std_logic;\r
23 PCI_AD : InOut std_logic_vector (31 downto 0);\r
24 PCI_PAR : InOut std_logic;\r
25 PCI_DEVSELn : Out std_logic;\r
26 PCI_INTAn : Out std_logic;\r
27 PCI_PERRn : Out std_logic;\r
28 PCI_SERRn : Out std_logic;\r
29 PCI_STOPn : Out std_logic;\r
30 PCI_TRDYn : Out std_logic;\r
377c0242 31 SERIAL_OUT : Out std_logic;\r
32 SPC_RDY_OUT : Out std_logic;\r
33 TB_IDSEL : Out std_logic;\r
34 TB_nDEVSEL : Out std_logic;\r
35 TB_nINTA : Out std_logic );\r
62946980 36end dhwk;\r
377c0242 37\r
62946980 38architecture SCHEMATIC of dhwk is\r
377c0242 39\r
40 SIGNAL gnd : std_logic := '0';\r
41 SIGNAL vcc : std_logic := '1';\r
42\r
43 signal READ_XX7_6 : std_logic;\r
44 signal RESERVE : std_logic;\r
45 signal SR_ERROR : std_logic;\r
46 signal R_ERROR : std_logic;\r
47 signal S_ERROR : std_logic;\r
48 signal WRITE_XX3_2 : std_logic;\r
49 signal WRITE_XX5_4 : std_logic;\r
50 signal WRITE_XX7_6 : std_logic;\r
51 signal READ_XX1_0 : std_logic;\r
52 signal READ_XX3_2 : std_logic;\r
53 signal INTAn : std_logic;\r
54 signal TRDYn : std_logic;\r
55 signal READ_XX5_4 : std_logic;\r
56 signal DEVSELn : std_logic;\r
57 signal FIFO_RDn : std_logic;\r
58 signal WRITE_XX1_0 : std_logic;\r
59 signal REG_OUT_XX6 : std_logic_vector (7 downto 0);\r
60 signal SYNC_FLAG : std_logic_vector (7 downto 0);\r
61 signal INT_REG : std_logic_vector (7 downto 0);\r
62 signal REVISON_ID : std_logic_vector (7 downto 0);\r
63 signal VENDOR_ID : std_logic_vector (15 downto 0);\r
64 signal READ_SEL : std_logic_vector (1 downto 0);\r
65 signal AD_REG : std_logic_vector (31 downto 0);\r
66 signal REG_OUT_XX7 : std_logic_vector (7 downto 0);\r
2825d08e 67 signal R_EFn : std_logic;\r
68 signal R_FFn : std_logic;\r
69 signal R_FIFO_Q_OUT : std_logic_vector (7 downto 0);\r
70 signal R_HFn : std_logic;\r
71 signal S_EFn : std_logic;\r
72 signal S_FFn : std_logic;\r
73 signal S_FIFO_Q_OUT : std_logic_vector (7 downto 0);\r
74 signal S_HFn : std_logic;\r
75 signal R_FIFO_D_IN : std_logic_vector (7 downto 0);\r
76 signal R_FIFO_READn : std_logic;\r
77 signal R_FIFO_RESETn : std_logic;\r
78 signal R_FIFO_RTn : std_logic;\r
79 signal R_FIFO_WRITEn : std_logic;\r
80 signal S_FIFO_D_IN : std_logic_vector (7 downto 0);\r
81 signal S_FIFO_READn : std_logic;\r
82 signal S_FIFO_RESETn : std_logic;\r
83 signal S_FIFO_RTn : std_logic;\r
84 signal S_FIFO_WRITEn : std_logic;\r
377c0242 85\r
86 component MESS_1_TB\r
87 Port ( DEVSELn : In std_logic;\r
88 INTAn : In std_logic;\r
89 KONST_1 : In std_logic;\r
90 PCI_IDSEL : In std_logic;\r
91 REG_OUT_XX7 : In std_logic_vector (7 downto 0);\r
92 TB_DEVSELn : Out std_logic;\r
93 TB_INTAn : Out std_logic;\r
94 TB_PCI_IDSEL : Out std_logic );\r
95 end component;\r
96\r
97 component VEN_REV_ID\r
98 Port ( REV_ID : Out std_logic_vector (7 downto 0);\r
99 VEN_ID : Out std_logic_vector (15 downto 0) );\r
100 end component;\r
101\r
102 component INTERRUPT\r
103 Port ( INT_IN_0 : In std_logic;\r
104 INT_IN_1 : In std_logic;\r
105 INT_IN_2 : In std_logic;\r
106 INT_IN_3 : In std_logic;\r
107 INT_IN_4 : In std_logic;\r
108 INT_IN_5 : In std_logic;\r
109 INT_IN_6 : In std_logic;\r
110 INT_IN_7 : In std_logic;\r
111 INT_MASKE : In std_logic_vector (7 downto 0);\r
112 INT_RES : In std_logic_vector (7 downto 0);\r
113 PCI_CLOCK : In std_logic;\r
114 PCI_RSTn : In std_logic;\r
115 READ_XX5_4 : In std_logic;\r
116 RESET : In std_logic;\r
117 TAST_RESn : In std_logic;\r
118 TAST_SETn : In std_logic;\r
119 TRDYn : In std_logic;\r
120 INT_REG : Out std_logic_vector (7 downto 0);\r
121 INTAn : Out std_logic;\r
122 PCI_INTAn : Out std_logic );\r
123 end component;\r
124\r
125 component FIFO_CONTROL\r
126 Port ( FIFO_RDn : In std_logic;\r
127 FLAG_IN_0 : In std_logic;\r
128 FLAG_IN_4 : In std_logic;\r
129 HOLD : In std_logic;\r
130 KONST_1 : In std_logic;\r
131 PCI_CLOCK : In std_logic;\r
132 PSC_ENABLE : In std_logic;\r
133 R_EFn : In std_logic;\r
134 R_FFn : In std_logic;\r
135 R_HFn : In std_logic;\r
136 RESET : In std_logic;\r
137 S_EFn : In std_logic;\r
138 S_FFn : In std_logic;\r
139 S_FIFO_Q_OUT : In std_logic_vector (7 downto 0);\r
140 S_HFn : In std_logic;\r
141 SERIAL_IN : In std_logic;\r
142 SPC_ENABLE : In std_logic;\r
143 SPC_RDY_IN : In std_logic;\r
144 WRITE_XX1_0 : In std_logic;\r
145 R_ERROR : Out std_logic;\r
146 R_FIFO_D_IN : Out std_logic_vector (7 downto 0);\r
147 R_FIFO_READn : Out std_logic;\r
148 R_FIFO_RESETn : Out std_logic;\r
149 R_FIFO_RETRANSMITn : Out std_logic;\r
150 R_FIFO_WRITEn : Out std_logic;\r
151 RESERVE : Out std_logic;\r
152 S_ERROR : Out std_logic;\r
153 S_FIFO_READn : Out std_logic;\r
154 S_FIFO_RESETn : Out std_logic;\r
155 S_FIFO_RETRANSMITn : Out std_logic;\r
156 S_FIFO_WRITEn : Out std_logic;\r
157 SERIAL_OUT : Out std_logic;\r
158 SPC_RDY_OUT : Out std_logic;\r
159 SR_ERROR : Out std_logic;\r
160 SYNC_FLAG : Out std_logic_vector (7 downto 0) );\r
161 end component;\r
162\r
163 component PCI_TOP\r
164 Port ( FLAG : In std_logic_vector (7 downto 0);\r
165 INT_REG : In std_logic_vector (7 downto 0);\r
166 PCI_CBEn : In std_logic_vector (3 downto 0);\r
167 PCI_CLOCK : In std_logic;\r
168 PCI_FRAMEn : In std_logic;\r
169 PCI_IDSEL : In std_logic;\r
170 PCI_IRDYn : In std_logic;\r
171 PCI_RSTn : In std_logic;\r
172 R_FIFO_Q : In std_logic_vector (7 downto 0);\r
173 REVISON_ID : In std_logic_vector (7 downto 0);\r
174 VENDOR_ID : In std_logic_vector (15 downto 0);\r
175 PCI_AD : InOut std_logic_vector (31 downto 0);\r
176 PCI_PAR : InOut std_logic;\r
177 AD_REG : Out std_logic_vector (31 downto 0);\r
178 DEVSELn : Out std_logic;\r
179 FIFO_RDn : Out std_logic;\r
180 PCI_DEVSELn : Out std_logic;\r
181 PCI_PERRn : Out std_logic;\r
182 PCI_SERRn : Out std_logic;\r
183 PCI_STOPn : Out std_logic;\r
184 PCI_TRDYn : Out std_logic;\r
185 READ_SEL : Out std_logic_vector (1 downto 0);\r
186 READ_XX1_0 : Out std_logic;\r
187 READ_XX3_2 : Out std_logic;\r
188 READ_XX5_4 : Out std_logic;\r
189 READ_XX7_6 : Out std_logic;\r
190 REG_OUT_XX0 : Out std_logic_vector (7 downto 0);\r
191 REG_OUT_XX6 : Out std_logic_vector (7 downto 0);\r
192 REG_OUT_XX7 : Out std_logic_vector (7 downto 0);\r
193 TRDYn : Out std_logic;\r
194 WRITE_XX1_0 : Out std_logic;\r
195 WRITE_XX3_2 : Out std_logic;\r
196 WRITE_XX5_4 : Out std_logic;\r
197 WRITE_XX7_6 : Out std_logic );\r
198 end component;\r
199\r
2825d08e 200component fifo_generator_v3_2\r
201 port (\r
202 clk: IN std_logic;\r
203 din: IN std_logic_VECTOR(7 downto 0);\r
204 rd_en: IN std_logic;\r
205 rst: IN std_logic;\r
206 wr_en: IN std_logic;\r
207 almost_empty: OUT std_logic;\r
208 almost_full: OUT std_logic;\r
209 dout: OUT std_logic_VECTOR(7 downto 0);\r
210 empty: OUT std_logic;\r
211 full: OUT std_logic;\r
212 prog_full: OUT std_logic);\r
213end component;\r
214\r
377c0242 215begin\r
216\r
217 I19 : MESS_1_TB\r
218 Port Map ( DEVSELn=>DEVSELn, INTAn=>INTAn, KONST_1=>KONST_1,\r
219 PCI_IDSEL=>PCI_IDSEL,\r
220 REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7(7 downto 0),\r
221 TB_DEVSELn=>TB_nDEVSEL, TB_INTAn=>TB_nINTA,\r
222 TB_PCI_IDSEL=>TB_IDSEL );\r
223 I18 : VEN_REV_ID\r
224 Port Map ( REV_ID(7 downto 0)=>REVISON_ID(7 downto 0),\r
225 VEN_ID(15 downto 0)=>VENDOR_ID(15 downto 0) );\r
226 I16 : INTERRUPT\r
227 Port Map ( INT_IN_0=>SYNC_FLAG(1), INT_IN_1=>SYNC_FLAG(6),\r
228 INT_IN_2=>KONST_1, INT_IN_3=>KONST_1, INT_IN_4=>KONST_1,\r
229 INT_IN_5=>KONST_1, INT_IN_6=>KONST_1, INT_IN_7=>KONST_1,\r
230 INT_MASKE(7 downto 0)=>REG_OUT_XX6(7 downto 0),\r
231 INT_RES(7 downto 0)=>AD_REG(7 downto 0),\r
232 PCI_CLOCK=>PCI_CLOCK, PCI_RSTn=>PCI_RSTn,\r
233 READ_XX5_4=>READ_XX5_4, RESET=>REG_OUT_XX7(0),\r
234 TAST_RESn=>TAST_RESn, TAST_SETn=>TAST_SETn,\r
235 TRDYn=>TRDYn, INT_REG(7 downto 0)=>INT_REG(7 downto 0),\r
236 INTAn=>INTAn, PCI_INTAn=>PCI_INTAn );\r
237 I14 : FIFO_CONTROL\r
238 Port Map ( FIFO_RDn=>FIFO_RDn, FLAG_IN_0=>R_ERROR,\r
239 FLAG_IN_4=>S_ERROR, HOLD=>READ_SEL(0), KONST_1=>KONST_1,\r
240 PCI_CLOCK=>PCI_CLOCK, PSC_ENABLE=>REG_OUT_XX7(1),\r
241 R_EFn=>R_EFn, R_FFn=>R_FFn, R_HFn=>R_HFn,\r
242 RESET=>REG_OUT_XX7(0), S_EFn=>S_EFn, S_FFn=>S_FFn,\r
243 S_FIFO_Q_OUT(7 downto 0)=>S_FIFO_Q_OUT(7 downto 0),\r
244 S_HFn=>S_HFn, SERIAL_IN=>SERIAL_IN,\r
245 SPC_ENABLE=>REG_OUT_XX7(2), SPC_RDY_IN=>SPC_RDY_IN,\r
246 WRITE_XX1_0=>WRITE_XX1_0, R_ERROR=>R_ERROR,\r
247 R_FIFO_D_IN(7 downto 0)=>R_FIFO_D_IN(7 downto 0),\r
248 R_FIFO_READn=>R_FIFO_READn,\r
249 R_FIFO_RESETn=>R_FIFO_RESETn,\r
250 R_FIFO_RETRANSMITn=>R_FIFO_RTn,\r
251 R_FIFO_WRITEn=>R_FIFO_WRITEn, RESERVE=>RESERVE,\r
252 S_ERROR=>S_ERROR, S_FIFO_READn=>S_FIFO_READn,\r
253 S_FIFO_RESETn=>S_FIFO_RESETn,\r
254 S_FIFO_RETRANSMITn=>S_FIFO_RTn,\r
255 S_FIFO_WRITEn=>S_FIFO_WRITEn, SERIAL_OUT=>SERIAL_OUT,\r
256 SPC_RDY_OUT=>SPC_RDY_OUT, SR_ERROR=>SR_ERROR,\r
257 SYNC_FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0) );\r
258 I1 : PCI_TOP\r
259 Port Map ( FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0),\r
260 INT_REG(7 downto 0)=>INT_REG(7 downto 0),\r
261 PCI_CBEn(3 downto 0)=>PCI_CBEn(3 downto 0),\r
262 PCI_CLOCK=>PCI_CLOCK, PCI_FRAMEn=>PCI_FRAMEn,\r
263 PCI_IDSEL=>PCI_IDSEL, PCI_IRDYn=>PCI_IRDYn,\r
264 PCI_RSTn=>PCI_RSTn,\r
265 R_FIFO_Q(7 downto 0)=>R_FIFO_Q_OUT(7 downto 0),\r
266 REVISON_ID(7 downto 0)=>REVISON_ID(7 downto 0),\r
267 VENDOR_ID(15 downto 0)=>VENDOR_ID(15 downto 0),\r
268 PCI_AD(31 downto 0)=>PCI_AD(31 downto 0),\r
269 PCI_PAR=>PCI_PAR,\r
270 AD_REG(31 downto 0)=>AD_REG(31 downto 0),\r
271 DEVSELn=>DEVSELn, FIFO_RDn=>FIFO_RDn,\r
272 PCI_DEVSELn=>PCI_DEVSELn, PCI_PERRn=>PCI_PERRn,\r
273 PCI_SERRn=>PCI_SERRn, PCI_STOPn=>PCI_STOPn,\r
274 PCI_TRDYn=>PCI_TRDYn,\r
275 READ_SEL(1 downto 0)=>READ_SEL(1 downto 0),\r
276 READ_XX1_0=>READ_XX1_0, READ_XX3_2=>READ_XX3_2,\r
277 READ_XX5_4=>READ_XX5_4, READ_XX7_6=>READ_XX7_6,\r
278 REG_OUT_XX0(7 downto 0)=>S_FIFO_D_IN(7 downto 0),\r
279 REG_OUT_XX6(7 downto 0)=>REG_OUT_XX6(7 downto 0),\r
280 REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7(7 downto 0),\r
281 TRDYn=>TRDYn, WRITE_XX1_0=>WRITE_XX1_0,\r
282 WRITE_XX3_2=>WRITE_XX3_2, WRITE_XX5_4=>WRITE_XX5_4,\r
283 WRITE_XX7_6=>WRITE_XX7_6 );\r
284\r
2825d08e 285receive_fifo : fifo_generator_v3_2\r
286 port map (\r
287 clk => PCI_CLOCK,\r
288 din => R_FIFO_D_IN,\r
289 rd_en => not R_FIFO_READn,\r
290 rst => not R_FIFO_RESETn,\r
291 wr_en => not R_FIFO_WRITEn,\r
292 dout => R_FIFO_Q_OUT,\r
293 empty => R_EFn,\r
294 full => R_FFn,\r
295 prog_full => R_HFn);\r
296\r
297send_fifo : fifo_generator_v3_2\r
298 port map (\r
299 clk => PCI_CLOCK,\r
300 din => S_FIFO_D_IN,\r
301 rd_en => not S_FIFO_READn,\r
302 rst => not S_FIFO_RESETn,\r
303 wr_en => not S_FIFO_WRITEn,\r
304 dout => S_FIFO_Q_OUT,\r
305 empty => S_EFn,\r
306 full => S_FFn,\r
307 prog_full => S_HFn);\r
377c0242 308end SCHEMATIC;\r
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