696ded12 |
1 | -- VHDL model created from schematic config_space_header.sch -- Jan 09 09:34:16 2007 |
2 | |
696ded12 |
3 | LIBRARY ieee; |
4 | |
5 | USE ieee.std_logic_1164.ALL; |
6 | USE ieee.numeric_std.ALL; |
7 | |
8 | |
9 | entity CONFIG_SPACE_HEADER is |
2612d712 |
10 | Port ( AD_REG : In std_logic_vector (31 downto 0); |
11 | ADDR_REG : In std_logic_vector (31 downto 0); |
12 | CBE_REGn : In std_logic_vector (3 downto 0); |
13 | CF_RD_COM : In std_logic; |
14 | CF_WR_COM : In std_logic; |
15 | IRDY_REGn : In std_logic; |
16 | PCI_CLOCK : In std_logic; |
17 | PCI_RSTn : In std_logic; |
18 | PERR : In std_logic; |
19 | REVISION_ID : In std_logic_vector (7 downto 0); |
20 | SERR : In std_logic; |
21 | TRDYn : In std_logic; |
22 | VENDOR_ID : In std_logic_vector (15 downto 0); |
23 | CONF_DATA : Out std_logic_vector (31 downto 0); |
24 | CONF_DATA_04H : Out std_logic_vector (31 downto 0); |
25 | CONF_DATA_10H : Out std_logic_vector (31 downto 0) ); |
696ded12 |
26 | end CONFIG_SPACE_HEADER; |
27 | |
28 | architecture SCHEMATIC of CONFIG_SPACE_HEADER is |
29 | |
ffdaba18 |
30 | constant CONF_DEVICE_ID :std_logic_vector(31 downto 16) := X"AFFE"; |
e90b12fe |
31 | --other comm. device |
32 | constant CONF_CLASS_CODE :std_logic_vector (31 downto 8) := X"078000"; |
ffdaba18 |
33 | |
6d5ab91b |
34 | signal CONF_MAX_LAT :std_logic_vector (31 downto 24); |
35 | signal CONF_MIN_GNT :std_logic_vector (23 downto 16); |
36 | signal CONF_INT_PIN :std_logic_vector (15 downto 8); |
37 | signal CONF_INT_LINE :std_logic_vector ( 7 downto 0); |
38 | |
2a7d0ce6 |
39 | signal CONF_BAS_ADDR_REG :std_logic_vector(31 downto 0); |
40 | |
2612d712 |
41 | SIGNAL gnd : std_logic := '0'; |
42 | SIGNAL vcc : std_logic := '1'; |
43 | |
44 | signal CONF_WR_04H : std_logic; |
45 | signal CONF_WR_10H : std_logic; |
46 | signal CONF_WR_3CH : std_logic; |
47 | signal CONF_READ_SEL : std_logic_vector (2 downto 0); |
2612d712 |
48 | signal CONF_DATA_04H_DUMMY : std_logic_vector (31 downto 0); |
49 | signal CONF_DATA_3CH : std_logic_vector (31 downto 0); |
50 | signal CONF_DATA_08H : std_logic_vector (31 downto 0); |
51 | signal CONF_DATA_00H : std_logic_vector (31 downto 0); |
52 | |
2612d712 |
53 | component CONFIG_RD_0 |
54 | Port ( ADDR_REG : In std_logic_vector (31 downto 0); |
55 | CF_RD_COM : In std_logic; |
56 | READ_SEL : Out std_logic_vector (2 downto 0) ); |
57 | end component; |
58 | |
59 | component CONFIG_WR_0 |
60 | Port ( ADDR_REG : In std_logic_vector (31 downto 0); |
61 | CF_WR_COM : In std_logic; |
62 | IRDY_REGn : In std_logic; |
63 | TRDYn : In std_logic; |
64 | CONF_WR_04H : Out std_logic; |
65 | CONF_WR_10H : Out std_logic; |
66 | CONF_WR_3CH : Out std_logic ); |
67 | end component; |
68 | |
2612d712 |
69 | component CONFIG_04H |
70 | Port ( AD_REG : In std_logic_vector (31 downto 0); |
71 | CBE_REGn : In std_logic_vector (3 downto 0); |
72 | CONF_WR_04H : In std_logic; |
73 | PCI_CLOCK : In std_logic; |
74 | PCI_RSTn : In std_logic; |
75 | PERR : In std_logic; |
76 | SERR : In std_logic; |
77 | CONF_DATA_04H : Out std_logic_vector (31 downto 0) ); |
78 | end component; |
696ded12 |
79 | |
80 | begin |
ffdaba18 |
81 | CONF_DATA_00H <= CONF_DEVICE_ID & VENDOR_ID; |
e90b12fe |
82 | CONF_DATA_08H <= CONF_CLASS_CODE & REVISION_ID; |
696ded12 |
83 | |
2612d712 |
84 | CONF_DATA_04H <= CONF_DATA_04H_DUMMY; |
2612d712 |
85 | |
6d5ab91b |
86 | CONF_MAX_LAT <= X"00"; |
87 | CONF_MIN_GNT <= X"00"; |
88 | -- CONF_INT_PIN <= X"00"; -- Interrupt - |
89 | CONF_INT_PIN <= X"01"; -- Interrupt A |
90 | -- CONF_INT_PIN <= X"02"; -- Interrupt B |
91 | -- CONF_INT_PIN <= X"03"; -- Interrupt C |
92 | -- CONF_INT_PIN <= X"04"; -- Interrupt D |
93 | -- CONF_INT_PIN <= X"05 - FF0"; -- Reserviert |
94 | CONF_DATA_3CH <= CONF_MAX_LAT & CONF_MIN_GNT & CONF_INT_PIN & CONF_INT_LINE; |
95 | |
2a7d0ce6 |
96 | CONF_BAS_ADDR_REG(1 downto 0) <= "01";-- Base Address Register for "I/O" |
97 | CONF_BAS_ADDR_REG(3 downto 2) <= "00";-- IO Bereich = 16 BYTE |
98 | CONF_DATA_10H <= CONF_BAS_ADDR_REG; |
99 | |
2612d712 |
100 | I9 : CONFIG_RD_0 |
101 | Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0), |
102 | CF_RD_COM=>CF_RD_COM, |
103 | READ_SEL(2 downto 0)=>CONF_READ_SEL(2 downto 0) ); |
104 | I8 : CONFIG_WR_0 |
105 | Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0), |
106 | CF_WR_COM=>CF_WR_COM, IRDY_REGn=>IRDY_REGn, |
107 | TRDYn=>TRDYn, CONF_WR_04H=>CONF_WR_04H, |
108 | CONF_WR_10H=>CONF_WR_10H, CONF_WR_3CH=>CONF_WR_3CH ); |
2612d712 |
109 | I2 : CONFIG_04H |
110 | Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0), |
111 | CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0), |
112 | CONF_WR_04H=>CONF_WR_04H, PCI_CLOCK=>PCI_CLOCK, |
113 | PCI_RSTn=>PCI_RSTn, PERR=>PERR, SERR=>SERR, |
114 | CONF_DATA_04H(31 downto 0)=>CONF_DATA_04H_DUMMY(31 downto 0) ); |
696ded12 |
115 | |
6d5ab91b |
116 | process (PCI_CLOCK,PCI_RSTn) |
117 | begin |
2a7d0ce6 |
118 | if PCI_RSTn = '0' then |
119 | CONF_INT_LINE <= (others => '0'); |
120 | |
121 | elsif (rising_edge(PCI_CLOCK)) then |
122 | if CONF_WR_3CH = '1'and CBE_REGn(0) = '0' then |
123 | CONF_INT_LINE(7 downto 0) <= AD_REG(7 downto 0); |
124 | end if; |
125 | end if; |
126 | end process; |
127 | |
128 | process (PCI_CLOCK,PCI_RSTn) |
129 | begin |
130 | |
131 | -- if PCI_RSTn = '0' then CONF_BAS_ADDR_REG(31 downto 2) <= (others =>'0'); |
132 | if PCI_RSTn = '0' then |
133 | CONF_BAS_ADDR_REG(31 downto 4) <= (others =>'0'); |
134 | |
135 | elsif (rising_edge(PCI_CLOCK)) then |
136 | |
137 | if CONF_WR_10H = '1'and CBE_REGn(3) = '0' then |
138 | CONF_BAS_ADDR_REG(31 downto 24) <= AD_REG(31 downto 24); |
139 | else |
140 | CONF_BAS_ADDR_REG(31 downto 24) <= CONF_BAS_ADDR_REG(31 downto 24); |
141 | end if; |
142 | |
143 | if CONF_WR_10H = '1'and CBE_REGn(2) = '0' then |
144 | CONF_BAS_ADDR_REG(23 downto 16) <= AD_REG(23 downto 16); |
145 | else |
146 | CONF_BAS_ADDR_REG(23 downto 16) <= CONF_BAS_ADDR_REG(23 downto 16); |
147 | end if; |
148 | |
149 | if CONF_WR_10H = '1'and CBE_REGn(1) = '0' then |
150 | CONF_BAS_ADDR_REG(15 downto 8) <= AD_REG(15 downto 8); |
151 | else |
152 | CONF_BAS_ADDR_REG(15 downto 8) <= CONF_BAS_ADDR_REG(15 downto 8); |
153 | end if; |
154 | |
155 | -- if CONF_WR_10H = '1'and CBE_REGn(0) = '0' then |
156 | -- CONF_BAS_ADDR_REG( 7 downto 2) <= AD_REG( 7 downto 2); |
157 | -- else |
158 | -- CONF_BAS_ADDR_REG( 7 downto 2) <= CONF_BAS_ADDR_REG( 7 downto 2); |
159 | -- end if; |
6d5ab91b |
160 | |
2a7d0ce6 |
161 | if CONF_WR_10H = '1'and CBE_REGn(0) = '0' then |
162 | CONF_BAS_ADDR_REG( 7 downto 4) <= AD_REG( 7 downto 4); |
163 | else |
164 | CONF_BAS_ADDR_REG( 7 downto 4) <= CONF_BAS_ADDR_REG( 7 downto 4); |
6d5ab91b |
165 | end if; |
2a7d0ce6 |
166 | end if; |
6d5ab91b |
167 | end process; |
696ded12 |
168 | end SCHEMATIC; |