[raggedstone] / dhwk / source / pci / config_space_header.vhd

-- VHDL model created from schematic config_space_header.sch -- Jan 09 09:34:16 2007

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;


entity CONFIG_SPACE_HEADER is
        Port ( AD_REG : In std_logic_vector (31 downto 0);
               ADDR_REG : In std_logic_vector (31 downto 0);
               CBE_REGn : In std_logic_vector (3 downto 0);
               CF_RD_COM : In std_logic;
               CF_WR_COM : In std_logic;
               IRDY_REGn : In std_logic;
               PCI_CLOCK : In std_logic;
               PCI_RSTn : In std_logic;
               PERR : In std_logic;
               REVISION_ID : In std_logic_vector (7 downto 0);
               SERR : In std_logic;
               TRDYn : In std_logic;
               VENDOR_ID : In std_logic_vector (15 downto 0);
               CONF_DATA : Out std_logic_vector (31 downto 0);
               CONF_DATA_04H : Out std_logic_vector (31 downto 0);
               CONF_DATA_10H : Out std_logic_vector (31 downto 0) );
end CONFIG_SPACE_HEADER;

architecture SCHEMATIC of CONFIG_SPACE_HEADER is

        constant CONF_DEVICE_ID :std_logic_vector(31 downto 16) := X"AFFE";
        --other comm. device
        constant CONF_CLASS_CODE :std_logic_vector (31 downto 8) := X"078000";

        signal CONF_MAX_LAT :std_logic_vector (31 downto 24);
        signal CONF_MIN_GNT :std_logic_vector (23 downto 16);
        signal CONF_INT_PIN :std_logic_vector (15 downto 8);
        signal CONF_INT_LINE :std_logic_vector ( 7 downto 0);

        signal CONF_BAS_ADDR_REG :std_logic_vector(31 downto 0);

        signal CONF_STATUS :std_logic_vector(31 downto 16);
        signal CONF_COMMAND :std_logic_vector(15 downto 0);

        -- PCI Configuration Space Header
        --
        -- \ Bit
        -- \
        --Address |31 24|23 16|15 8|7 0|
        -----------------------------------------------------------------
        --00 |Device ID |Vendor ID |
        --04 |Status |Command |
        --08 |Class Code |Revision ID |
        --0C |BIST |Header Type |Latency T. |Cache L.S. |
        --10-24 |Base Address Register |
        --28 |Cardbus CIS Pointer |
        --2C |Subsystem ID |Subsystem Vendor ID |
        --30 |Expansion ROM Base Address |
        --34 |Reserved |
        --38 |Reserved |
        --3C |Max_Lat |Min_Gnt |Int_Pin |Int_Line |
        --40-FF | |
        -----------------------------------------------------------------


        --PCI Bus Commands
        --C/BE[3..0] Command Type
        --------------------------------------
        -- 0000 Interrupt Acknowledge
        -- 0001 Special Cycle
        -- 0010 I/O Read
        -- 0011 I/O Write
        -- 0100 Reserved
        -- 0101 Reserved
        -- 0110 Memory Read
        -- 0111 Memory Write
        --
        -- 1000 Reserved
        -- 1001 Reserved
        -- 1010 Configuration Read
        -- 1011 Configuration Write
        -- 1100 Memory Read Multiple
        -- 1101 Dual Address Cycle
        -- 1110 Memory Read Line
        -- 1111 Memory Write and Invalidate


        --PCI Byte Enable
        --C/BE[3..0] gueltige Datenbits
        -------------------------------
        -- 0000 AD 31..0
        -- 1000 AD 23..0
        -- 1100 AD 15..0
        -- 1110 AD 7..0

        constant CMD_INT_ACK :std_logic_vector(3 downto 0) := "0000";
        constant CMD_SP_CYC :std_logic_vector(3 downto 0) := "0001";
        constant CMD_IO_READ :std_logic_vector(3 downto 0) := "0010";
        constant CMD_IO_WRITE :std_logic_vector(3 downto 0) := "0011";
        constant CMD_RES_4 :std_logic_vector(3 downto 0) := "0100";
        constant CMD_RES_5 :std_logic_vector(3 downto 0) := "0101";
        constant CMD_MEM_READ :std_logic_vector(3 downto 0) := "0110";
        constant CMD_MEM_WRITE :std_logic_vector(3 downto 0) := "0111";
        constant CMD_RES_8 :std_logic_vector(3 downto 0) := "1000";
        constant CMD_RES_9 :std_logic_vector(3 downto 0) := "1001";
        constant CMD_CONF_READ :std_logic_vector(3 downto 0) := "1010";
        constant CMD_CONF_WRITE :std_logic_vector(3 downto 0) := "1011";
        constant CMD_MEM_READ_M :std_logic_vector(3 downto 0) := "1100";
        constant CMD_DU_ADR_CYC :std_logic_vector(3 downto 0) := "1101";
        constant CMD_MEN_READ_L :std_logic_vector(3 downto 0) := "1110";
        constant CMD_MEM_WRITE_I :std_logic_vector(3 downto 0) := "1111";

        signal CONFIG_ADDR :std_logic_vector(7 downto 0);
        signal CONFIG_WRITE :std_logic_vector(3 downto 0);

        SIGNAL gnd : std_logic := '0';
        SIGNAL vcc : std_logic := '1';

        signal CONF_WR_04H : std_logic;
        signal CONF_WR_10H : std_logic;
        signal CONF_WR_3CH : std_logic;
        signal CONF_READ_SEL : std_logic_vector (2 downto 0);
        signal CONF_DATA_3CH : std_logic_vector (31 downto 0);
        signal CONF_DATA_08H : std_logic_vector (31 downto 0);
        signal CONF_DATA_00H : std_logic_vector (31 downto 0);

begin
        CONF_DATA_00H <= CONF_DEVICE_ID & VENDOR_ID;
        CONF_DATA_08H <= CONF_CLASS_CODE & REVISION_ID;
        CONF_DATA_04H <= CONF_STATUS & CONF_COMMAND;

        CONF_MAX_LAT <= X"00";
        CONF_MIN_GNT <= X"00";
        -- CONF_INT_PIN <= X"00"; -- Interrupt -
        CONF_INT_PIN <= X"01"; -- Interrupt A
        -- CONF_INT_PIN <= X"02"; -- Interrupt B
        -- CONF_INT_PIN <= X"03"; -- Interrupt C
        -- CONF_INT_PIN <= X"04"; -- Interrupt D
        -- CONF_INT_PIN <= X"05 - FF0"; -- Reserviert
        CONF_DATA_3CH <= CONF_MAX_LAT & CONF_MIN_GNT & CONF_INT_PIN & CONF_INT_LINE;

        CONF_BAS_ADDR_REG(1 downto 0) <= "01";-- Base Address Register for "I/O"
        CONF_BAS_ADDR_REG(3 downto 2) <= "00";-- IO Bereich = 16 BYTE
        CONF_DATA_10H <= CONF_BAS_ADDR_REG;

        process (PCI_CLOCK,PCI_RSTn)
        begin
        if PCI_RSTn = '0' then
                CONF_INT_LINE <= (others => '0');

        elsif (rising_edge(PCI_CLOCK)) then
                if CONF_WR_3CH = '1'and CBE_REGn(0) = '0' then
                        CONF_INT_LINE(7 downto 0) <= AD_REG(7 downto 0);
                end if;
        end if;
        end process;

        process (PCI_CLOCK,PCI_RSTn)
        begin

        -- if PCI_RSTn = '0' then CONF_BAS_ADDR_REG(31 downto 2) <= (others =>'0');
        if PCI_RSTn = '0' then
                CONF_BAS_ADDR_REG(31 downto 4) <= (others =>'0');

        elsif (rising_edge(PCI_CLOCK)) then

                if CONF_WR_10H = '1'and CBE_REGn(3) = '0' then
                        CONF_BAS_ADDR_REG(31 downto 24) <= AD_REG(31 downto 24);
                else
                        CONF_BAS_ADDR_REG(31 downto 24) <= CONF_BAS_ADDR_REG(31 downto 24);
                end if;

                if CONF_WR_10H = '1'and CBE_REGn(2) = '0' then
                        CONF_BAS_ADDR_REG(23 downto 16) <= AD_REG(23 downto 16);
                else
                        CONF_BAS_ADDR_REG(23 downto 16) <= CONF_BAS_ADDR_REG(23 downto 16);
                end if;

                if CONF_WR_10H = '1'and CBE_REGn(1) = '0' then
                        CONF_BAS_ADDR_REG(15 downto 8) <= AD_REG(15 downto 8);
                else
                        CONF_BAS_ADDR_REG(15 downto 8) <= CONF_BAS_ADDR_REG(15 downto 8);
                end if;

                -- if CONF_WR_10H = '1'and CBE_REGn(0) = '0' then
                --         CONF_BAS_ADDR_REG( 7 downto 2) <= AD_REG( 7 downto 2);
                -- else
                --         CONF_BAS_ADDR_REG( 7 downto 2) <= CONF_BAS_ADDR_REG( 7 downto 2);
                -- end if;

                if CONF_WR_10H = '1'and CBE_REGn(0) = '0' then
                        CONF_BAS_ADDR_REG( 7 downto 4) <= AD_REG( 7 downto 4);
                else
                        CONF_BAS_ADDR_REG( 7 downto 4) <= CONF_BAS_ADDR_REG( 7 downto 4);
                end if;
        end if;
        end process;

        --*******************************************************************
        --************* PCI Configuration Space Header "STATUS" *************
        --*******************************************************************

        CONF_STATUS(20 downto 16) <= "00000";-- Reserved
        CONF_STATUS(21 ) <= '0';-- MAS/TAR: "R_O" :'0'= 33MHz / '1'= 66MHz
        CONF_STATUS(22 ) <= '0';-- MAS/TAR: "R_O"
        CONF_STATUS(23 ) <= '0';-- ???/???: "R_O" : fast back-to-back
        CONF_STATUS(24 ) <= '0';-- Master :
        --CONF_STATUS(26 downto 25) <= "00";-- Mas/Tar: "R_O" : timing fast for "DEVSEL"
        CONF_STATUS(26 downto 25) <= "01";-- Mas/Tar: "R_O" : timing medium for "DEVSEL"
        --CONF_STATUS(26 downto 25) <= "10";-- Mas/Tar: "R_O" : timing slow for "DEVSEL"
        --CONF_STATUS(26 downto 25) <= "11";-- Mas/Tar: "R_O" : reserved
        CONF_STATUS(27 ) <= '0';-- Target : "R_W" : Taget-Abort
        CONF_STATUS(28 ) <= '0';-- Master : "R_W" : Taget-Abort
        CONF_STATUS(29 ) <= '0';-- Master : "R_W" : Master-Abort
        --CONF_STATUS(30 ) <= SERR;-- Mas/Tar: "R_W" : SERR
        --CONF_STATUS(31 ) <= PERR;-- Mas/Tar: "R_W" : PERR

        process (PCI_CLOCK,PCI_RSTn)
        begin
        if PCI_RSTn = '0' then
                CONF_STATUS(30) <= '0';
                CONF_STATUS(31) <= '0';

        elsif (rising_edge(PCI_CLOCK)) then
                if CONF_WR_04H = '1' and CBE_REGn(3) = '0' then
                        CONF_STATUS(30) <= not (AD_REG(30) and CONF_STATUS(30));
                        CONF_STATUS(31) <= not (AD_REG(31) and CONF_STATUS(31));

                else
                        CONF_STATUS(30) <= SERR or CONF_STATUS(30);
                        CONF_STATUS(31) <= PERR or CONF_STATUS(31);

                end if;
        end if;
        end process;

        --*******************************************************************
        --*********** PCI Configuration Space Header "COMMAND" **************
        --*******************************************************************

        -- CONF_COMMAND( 0) <= '0';-- I/O Space accesses ???
        -- CONF_COMMAND( 1) <= '0';-- Mem Space accesses ???
        -- CONF_COMMAND( 2) <= '0';-- abillity to act as a master on the PCI bus
        -- CONF_COMMAND( 3) <= '0';-- Special Cycle ???
        -- CONF_COMMAND( 4) <= '0';-- Master ???
        -- CONF_COMMAND( 5) <= '0';-- VGA ???
        -- CONF_COMMAND( 6) <= '0';-- Party checking enable/disable
        CONF_COMMAND( 7) <= '0';-- address/data stepping ???
        -- CONF_COMMAND( 8) <= '0';-- enable/disable "PCI_SERRn"
        -- CONF_COMMAND( 9) <= '0';-- fast back-to-back
        -- CONF_COMMAND(10) <= '0';-- Reserved
        -- CONF_COMMAND(11) <= '0';-- Reserved
        -- CONF_COMMAND(12) <= '0';-- Reserved
        -- CONF_COMMAND(13) <= '0';-- Reserved
        -- CONF_COMMAND(14) <= '0';-- Reserved
        -- CONF_COMMAND(15) <= '0';-- Reserved

        process (PCI_CLOCK,PCI_RSTn)
        begin
                if PCI_RSTn = '0' then
                        CONF_COMMAND(15 downto 8) <= (others =>'0');
                        CONF_COMMAND( 6 downto 0) <= (others =>'0');

                elsif (rising_edge(PCI_CLOCK)) then

                        if CONF_WR_04H = '1'and CBE_REGn(1) = '0' then
                                CONF_COMMAND(15 downto 8) <= AD_REG(15 downto 8);
                        else
                                CONF_COMMAND(15 downto 8) <= CONF_COMMAND(15 downto 8);
                        end if;

                        if CONF_WR_04H = '1'and CBE_REGn(0) = '0' then
                                CONF_COMMAND( 6 downto 0) <= AD_REG( 6 downto 0);
                        else
                                CONF_COMMAND( 6 downto 0) <= CONF_COMMAND( 6 downto 0);
                        end if;
                end if;
        end process;


        --*******************************************************************
        --******************* PCI Write Configuration Address ***************
        --*******************************************************************

        CONFIG_ADDR(7 downto 0) <= ADDR_REG(7 downto 0);


        process (CF_WR_COM,IRDY_REGn,TRDYn,CONFIG_ADDR)
        begin

                if CF_WR_COM = '1' and IRDY_REGn = '0' and TRDYn = '0' then

                        if CONFIG_ADDR = X"04" then
                                CONFIG_WRITE <= "0001";

                        elsif CONFIG_ADDR = X"10" then
                                CONFIG_WRITE <= "0010";

                        elsif CONFIG_ADDR = X"3C" then
                                CONFIG_WRITE <= "0100";

                        -- elsif CONFIG_ADDR = X"40" then
                        --         CONFIG_WRITE <= "1000";
                        else
                                CONFIG_WRITE <= "0000";
                        end if;
                else
                        CONFIG_WRITE <= "0000";
                end if;
        end process;

        CONF_WR_04H <= CONFIG_WRITE(0);
        CONF_WR_10H <= CONFIG_WRITE(1);
        CONF_WR_3CH <= CONFIG_WRITE(2);
        --CONF_WR_40H <= CONFIG_WRITE(3);

        process (CF_RD_COM, CONFIG_ADDR)
        begin

                if CF_RD_COM = '1' then
                        if CONFIG_ADDR = X"00" then
                                CONF_READ_SEL <= "000";

                        elsif CONFIG_ADDR = X"04" then
                                CONF_READ_SEL <= "001";

                        elsif CONFIG_ADDR = X"08" then
                                CONF_READ_SEL <= "010";

                        elsif CONFIG_ADDR = X"10" then
                                CONF_READ_SEL <= "011";

                        elsif CONFIG_ADDR = X"3C" then
                                CONF_READ_SEL <= "100";

                        elsif CONFIG_ADDR = X"40" then
                                CONF_READ_SEL <= "101";

                        else
                                CONF_READ_SEL <= "111";
                        end if;
                else
                        CONF_READ_SEL <= "111";
                end if;
        end process;

end SCHEMATIC;
Commit	Line	Data
696ded12	1	-- VHDL model created from schematic config_space_header.sch -- Jan 09 09:34:16 2007
696ded12	2
696ded12	3	LIBRARY ieee;
	4
	5	USE ieee.std_logic_1164.ALL;
	6	USE ieee.numeric_std.ALL;
	7
	8
	9	entity CONFIG_SPACE_HEADER is
2612d712	10	Port ( AD_REG : In std_logic_vector (31 downto 0);
	11	ADDR_REG : In std_logic_vector (31 downto 0);
	12	CBE_REGn : In std_logic_vector (3 downto 0);
	13	CF_RD_COM : In std_logic;
	14	CF_WR_COM : In std_logic;
	15	IRDY_REGn : In std_logic;
	16	PCI_CLOCK : In std_logic;
	17	PCI_RSTn : In std_logic;
	18	PERR : In std_logic;
	19	REVISION_ID : In std_logic_vector (7 downto 0);
	20	SERR : In std_logic;
	21	TRDYn : In std_logic;
	22	VENDOR_ID : In std_logic_vector (15 downto 0);
	23	CONF_DATA : Out std_logic_vector (31 downto 0);
	24	CONF_DATA_04H : Out std_logic_vector (31 downto 0);
	25	CONF_DATA_10H : Out std_logic_vector (31 downto 0) );
696ded12	26	end CONFIG_SPACE_HEADER;
	27
	28	architecture SCHEMATIC of CONFIG_SPACE_HEADER is
	29
ffdaba18	30	constant CONF_DEVICE_ID :std_logic_vector(31 downto 16) := X"AFFE";
e90b12fe	31	--other comm. device
e90b12fe	32	constant CONF_CLASS_CODE :std_logic_vector (31 downto 8) := X"078000";
ffdaba18	33
6d5ab91b	34	signal CONF_MAX_LAT :std_logic_vector (31 downto 24);
	35	signal CONF_MIN_GNT :std_logic_vector (23 downto 16);
	36	signal CONF_INT_PIN :std_logic_vector (15 downto 8);
	37	signal CONF_INT_LINE :std_logic_vector ( 7 downto 0);
	38
2a7d0ce6	39	signal CONF_BAS_ADDR_REG :std_logic_vector(31 downto 0);
2a7d0ce6	40
816293e0	41	signal CONF_STATUS :std_logic_vector(31 downto 16);
	42	signal CONF_COMMAND :std_logic_vector(15 downto 0);
	43
7f64ffff	44	-- PCI Configuration Space Header
	45	--
	46	-- \ Bit
	47	-- \
	48	--Address \|31 24\|23 16\|15 8\|7 0\|
	49	-----------------------------------------------------------------
	50	--00 \|Device ID \|Vendor ID \|
	51	--04 \|Status \|Command \|
	52	--08 \|Class Code \|Revision ID \|
	53	--0C \|BIST \|Header Type \|Latency T. \|Cache L.S. \|
	54	--10-24 \|Base Address Register \|
	55	--28 \|Cardbus CIS Pointer \|
	56	--2C \|Subsystem ID \|Subsystem Vendor ID \|
	57	--30 \|Expansion ROM Base Address \|
	58	--34 \|Reserved \|
	59	--38 \|Reserved \|
	60	--3C \|Max_Lat \|Min_Gnt \|Int_Pin \|Int_Line \|
	61	--40-FF \| \|
	62	-----------------------------------------------------------------
	63
	64
	65	--PCI Bus Commands
	66	--C/BE[3..0] Command Type
	67	--------------------------------------
	68	-- 0000 Interrupt Acknowledge
	69	-- 0001 Special Cycle
	70	-- 0010 I/O Read
	71	-- 0011 I/O Write
	72	-- 0100 Reserved
	73	-- 0101 Reserved
	74	-- 0110 Memory Read
	75	-- 0111 Memory Write
	76	--
	77	-- 1000 Reserved
	78	-- 1001 Reserved
	79	-- 1010 Configuration Read
	80	-- 1011 Configuration Write
	81	-- 1100 Memory Read Multiple
	82	-- 1101 Dual Address Cycle
	83	-- 1110 Memory Read Line
	84	-- 1111 Memory Write and Invalidate
	85
	86
	87	--PCI Byte Enable
	88	--C/BE[3..0] gueltige Datenbits
	89	-------------------------------
	90	-- 0000 AD 31..0
	91	-- 1000 AD 23..0
	92	-- 1100 AD 15..0
	93	-- 1110 AD 7..0
	94
	95	constant CMD_INT_ACK :std_logic_vector(3 downto 0) := "0000";
	96	constant CMD_SP_CYC :std_logic_vector(3 downto 0) := "0001";
	97	constant CMD_IO_READ :std_logic_vector(3 downto 0) := "0010";
	98	constant CMD_IO_WRITE :std_logic_vector(3 downto 0) := "0011";
	99	constant CMD_RES_4 :std_logic_vector(3 downto 0) := "0100";
	100	constant CMD_RES_5 :std_logic_vector(3 downto 0) := "0101";
	101	constant CMD_MEM_READ :std_logic_vector(3 downto 0) := "0110";
	102	constant CMD_MEM_WRITE :std_logic_vector(3 downto 0) := "0111";
	103	constant CMD_RES_8 :std_logic_vector(3 downto 0) := "1000";
	104	constant CMD_RES_9 :std_logic_vector(3 downto 0) := "1001";
	105	constant CMD_CONF_READ :std_logic_vector(3 downto 0) := "1010";
	106	constant CMD_CONF_WRITE :std_logic_vector(3 downto 0) := "1011";
	107	constant CMD_MEM_READ_M :std_logic_vector(3 downto 0) := "1100";
108	constant CMD_DU_ADR_CYC :std_logic_vector(3 downto 0) := "1101";
109	constant CMD_MEN_READ_L :std_logic_vector(3 downto 0) := "1110";
110	constant CMD_MEM_WRITE_I :std_logic_vector(3 downto 0) := "1111";
111
112	signal CONFIG_ADDR :std_logic_vector(7 downto 0);
113	signal CONFIG_WRITE :std_logic_vector(3 downto 0);
114
2612d712	115	SIGNAL gnd : std_logic := '0';
	116	SIGNAL vcc : std_logic := '1';
	117
	118	signal CONF_WR_04H : std_logic;
	119	signal CONF_WR_10H : std_logic;
	120	signal CONF_WR_3CH : std_logic;
	121	signal CONF_READ_SEL : std_logic_vector (2 downto 0);
2612d712	122	signal CONF_DATA_3CH : std_logic_vector (31 downto 0);
	123	signal CONF_DATA_08H : std_logic_vector (31 downto 0);
	124	signal CONF_DATA_00H : std_logic_vector (31 downto 0);
	125
696ded12	126	begin
ffdaba18	127	CONF_DATA_00H <= CONF_DEVICE_ID & VENDOR_ID;
e90b12fe	128	CONF_DATA_08H <= CONF_CLASS_CODE & REVISION_ID;
816293e0	129	CONF_DATA_04H <= CONF_STATUS & CONF_COMMAND;
2612d712	130
6d5ab91b	131	CONF_MAX_LAT <= X"00";
	132	CONF_MIN_GNT <= X"00";
	133	-- CONF_INT_PIN <= X"00"; -- Interrupt -
	134	CONF_INT_PIN <= X"01"; -- Interrupt A
	135	-- CONF_INT_PIN <= X"02"; -- Interrupt B
	136	-- CONF_INT_PIN <= X"03"; -- Interrupt C
	137	-- CONF_INT_PIN <= X"04"; -- Interrupt D
	138	-- CONF_INT_PIN <= X"05 - FF0"; -- Reserviert
	139	CONF_DATA_3CH <= CONF_MAX_LAT & CONF_MIN_GNT & CONF_INT_PIN & CONF_INT_LINE;
	140
2a7d0ce6	141	CONF_BAS_ADDR_REG(1 downto 0) <= "01";-- Base Address Register for "I/O"
	142	CONF_BAS_ADDR_REG(3 downto 2) <= "00";-- IO Bereich = 16 BYTE
	143	CONF_DATA_10H <= CONF_BAS_ADDR_REG;
	144
6d5ab91b	145	process (PCI_CLOCK,PCI_RSTn)
6d5ab91b	146	begin
2a7d0ce6	147	if PCI_RSTn = '0' then
	148	CONF_INT_LINE <= (others => '0');
	149
	150	elsif (rising_edge(PCI_CLOCK)) then
	151	if CONF_WR_3CH = '1'and CBE_REGn(0) = '0' then
	152	CONF_INT_LINE(7 downto 0) <= AD_REG(7 downto 0);
	153	end if;
	154	end if;
	155	end process;
	156
	157	process (PCI_CLOCK,PCI_RSTn)
	158	begin
	159
	160	-- if PCI_RSTn = '0' then CONF_BAS_ADDR_REG(31 downto 2) <= (others =>'0');
	161	if PCI_RSTn = '0' then
	162	CONF_BAS_ADDR_REG(31 downto 4) <= (others =>'0');
	163
	164	elsif (rising_edge(PCI_CLOCK)) then
	165
	166	if CONF_WR_10H = '1'and CBE_REGn(3) = '0' then
	167	CONF_BAS_ADDR_REG(31 downto 24) <= AD_REG(31 downto 24);
	168	else
	169	CONF_BAS_ADDR_REG(31 downto 24) <= CONF_BAS_ADDR_REG(31 downto 24);
	170	end if;
	171
	172	if CONF_WR_10H = '1'and CBE_REGn(2) = '0' then
	173	CONF_BAS_ADDR_REG(23 downto 16) <= AD_REG(23 downto 16);
	174	else
	175	CONF_BAS_ADDR_REG(23 downto 16) <= CONF_BAS_ADDR_REG(23 downto 16);
	176	end if;
	177
	178	if CONF_WR_10H = '1'and CBE_REGn(1) = '0' then
	179	CONF_BAS_ADDR_REG(15 downto 8) <= AD_REG(15 downto 8);
	180	else
	181	CONF_BAS_ADDR_REG(15 downto 8) <= CONF_BAS_ADDR_REG(15 downto 8);
	182	end if;
	183
	184	-- if CONF_WR_10H = '1'and CBE_REGn(0) = '0' then
	185	-- CONF_BAS_ADDR_REG( 7 downto 2) <= AD_REG( 7 downto 2);
	186	-- else
	187	-- CONF_BAS_ADDR_REG( 7 downto 2) <= CONF_BAS_ADDR_REG( 7 downto 2);
	188	-- end if;
6d5ab91b	189
2a7d0ce6	190	if CONF_WR_10H = '1'and CBE_REGn(0) = '0' then
	191	CONF_BAS_ADDR_REG( 7 downto 4) <= AD_REG( 7 downto 4);
	192	else
	193	CONF_BAS_ADDR_REG( 7 downto 4) <= CONF_BAS_ADDR_REG( 7 downto 4);
6d5ab91b	194	end if;
2a7d0ce6	195	end if;
6d5ab91b	196	end process;
816293e0	197
	198	--*******************************************************************
	199	--*********** PCI Configuration Space Header "STATUS" ***********
	200	--*******************************************************************
	201
	202	CONF_STATUS(20 downto 16) <= "00000";-- Reserved
	203	CONF_STATUS(21 ) <= '0';-- MAS/TAR: "R_O" :'0'= 33MHz / '1'= 66MHz
	204	CONF_STATUS(22 ) <= '0';-- MAS/TAR: "R_O"
	205	CONF_STATUS(23 ) <= '0';-- ???/???: "R_O" : fast back-to-back
	206	CONF_STATUS(24 ) <= '0';-- Master :
	207	--CONF_STATUS(26 downto 25) <= "00";-- Mas/Tar: "R_O" : timing fast for "DEVSEL"
	208	CONF_STATUS(26 downto 25) <= "01";-- Mas/Tar: "R_O" : timing medium for "DEVSEL"
	209	--CONF_STATUS(26 downto 25) <= "10";-- Mas/Tar: "R_O" : timing slow for "DEVSEL"
	210	--CONF_STATUS(26 downto 25) <= "11";-- Mas/Tar: "R_O" : reserved
	211	CONF_STATUS(27 ) <= '0';-- Target : "R_W" : Taget-Abort
	212	CONF_STATUS(28 ) <= '0';-- Master : "R_W" : Taget-Abort
	213	CONF_STATUS(29 ) <= '0';-- Master : "R_W" : Master-Abort
	214	--CONF_STATUS(30 ) <= SERR;-- Mas/Tar: "R_W" : SERR
	215	--CONF_STATUS(31 ) <= PERR;-- Mas/Tar: "R_W" : PERR
	216
	217	process (PCI_CLOCK,PCI_RSTn)
	218	begin
	219	if PCI_RSTn = '0' then
	220	CONF_STATUS(30) <= '0';
	221	CONF_STATUS(31) <= '0';
	222
	223	elsif (rising_edge(PCI_CLOCK)) then
	224	if CONF_WR_04H = '1' and CBE_REGn(3) = '0' then
	225	CONF_STATUS(30) <= not (AD_REG(30) and CONF_STATUS(30));
	226	CONF_STATUS(31) <= not (AD_REG(31) and CONF_STATUS(31));
	227
	228	else
	229	CONF_STATUS(30) <= SERR or CONF_STATUS(30);
	230	CONF_STATUS(31) <= PERR or CONF_STATUS(31);
	231
	232	end if;
	233	end if;
	234	end process;
	235
	236	--*******************************************************************
	237	--********* PCI Configuration Space Header "COMMAND" ************
	238	--*******************************************************************
	239
	240	-- CONF_COMMAND( 0) <= '0';-- I/O Space accesses ???
	241	-- CONF_COMMAND( 1) <= '0';-- Mem Space accesses ???
	242	-- CONF_COMMAND( 2) <= '0';-- abillity to act as a master on the PCI bus
	243	-- CONF_COMMAND( 3) <= '0';-- Special Cycle ???
	244	-- CONF_COMMAND( 4) <= '0';-- Master ???
	245	-- CONF_COMMAND( 5) <= '0';-- VGA ???
	246	-- CONF_COMMAND( 6) <= '0';-- Party checking enable/disable
	247	CONF_COMMAND( 7) <= '0';-- address/data stepping ???
	248	-- CONF_COMMAND( 8) <= '0';-- enable/disable "PCI_SERRn"
	249	-- CONF_COMMAND( 9) <= '0';-- fast back-to-back
	250	-- CONF_COMMAND(10) <= '0';-- Reserved
	251	-- CONF_COMMAND(11) <= '0';-- Reserved
	252	-- CONF_COMMAND(12) <= '0';-- Reserved
	253	-- CONF_COMMAND(13) <= '0';-- Reserved
	254	-- CONF_COMMAND(14) <= '0';-- Reserved
	255	-- CONF_COMMAND(15) <= '0';-- Reserved
	256
	257	process (PCI_CLOCK,PCI_RSTn)
	258	begin
	259	if PCI_RSTn = '0' then
	260	CONF_COMMAND(15 downto 8) <= (others =>'0');
261	CONF_COMMAND( 6 downto 0) <= (others =>'0');
262
263	elsif (rising_edge(PCI_CLOCK)) then
264
265	if CONF_WR_04H = '1'and CBE_REGn(1) = '0' then
266	CONF_COMMAND(15 downto 8) <= AD_REG(15 downto 8);
267	else
268	CONF_COMMAND(15 downto 8) <= CONF_COMMAND(15 downto 8);
269	end if;
270
271	if CONF_WR_04H = '1'and CBE_REGn(0) = '0' then
272	CONF_COMMAND( 6 downto 0) <= AD_REG( 6 downto 0);
273	else
274	CONF_COMMAND( 6 downto 0) <= CONF_COMMAND( 6 downto 0);
275	end if;
276	end if;
277	end process;
7f64ffff	278
	279
	280	--*******************************************************************
	281	--***************** PCI Write Configuration Address *************
	282	--*******************************************************************
	283
	284	CONFIG_ADDR(7 downto 0) <= ADDR_REG(7 downto 0);
	285
	286
	287	process (CF_WR_COM,IRDY_REGn,TRDYn,CONFIG_ADDR)
	288	begin
	289
	290	if CF_WR_COM = '1' and IRDY_REGn = '0' and TRDYn = '0' then
	291
	292	if CONFIG_ADDR = X"04" then
	293	CONFIG_WRITE <= "0001";
	294
	295	elsif CONFIG_ADDR = X"10" then
	296	CONFIG_WRITE <= "0010";
	297
	298	elsif CONFIG_ADDR = X"3C" then
	299	CONFIG_WRITE <= "0100";
	300
	301	-- elsif CONFIG_ADDR = X"40" then
	302	-- CONFIG_WRITE <= "1000";
	303	else
	304	CONFIG_WRITE <= "0000";
	305	end if;
	306	else
	307	CONFIG_WRITE <= "0000";
	308	end if;
	309	end process;
	310
	311	CONF_WR_04H <= CONFIG_WRITE(0);
	312	CONF_WR_10H <= CONFIG_WRITE(1);
	313	CONF_WR_3CH <= CONFIG_WRITE(2);
	314	--CONF_WR_40H <= CONFIG_WRITE(3);
	315
2e92b1a1	316	process (CF_RD_COM, CONFIG_ADDR)
	317	begin
	318
	319	if CF_RD_COM = '1' then
	320	if CONFIG_ADDR = X"00" then
	321	CONF_READ_SEL <= "000";
	322
	323	elsif CONFIG_ADDR = X"04" then
	324	CONF_READ_SEL <= "001";
	325
	326	elsif CONFIG_ADDR = X"08" then
	327	CONF_READ_SEL <= "010";
	328
	329	elsif CONFIG_ADDR = X"10" then
	330	CONF_READ_SEL <= "011";
	331
	332	elsif CONFIG_ADDR = X"3C" then
	333	CONF_READ_SEL <= "100";
	334
	335	elsif CONFIG_ADDR = X"40" then
	336	CONF_READ_SEL <= "101";
	337
	338	else
	339	CONF_READ_SEL <= "111";
	340	end if;
	341	else
	342	CONF_READ_SEL <= "111";
	343	end if;
	344	end process;
	345
696ded12	346	end SCHEMATIC;