[raggedstone] / dhwk / source / INTERRUPT.vhd

-- J.STELZNER\r
-- INFORMATIK-3 LABOR\r
-- 23.08.2006\r
-- File: INTERRUPT.VHD\r
\r
library ieee;\r
use ieee.std_logic_1164.all;\r
\r
entity INTERRUPT is\r
	port\r
	(\r
	PCI_CLOCK		:in		std_logic;\r
	PCI_RSTn		:in 	std_logic; -- PCI reset is asynchron (low active)\r
	RESET				:in 	std_logic;\r
	TAST_SETn		:in 	std_logic;\r
	TAST_RESn		:in 	std_logic;\r
	INT_IN_0		:in		std_logic;\r
	INT_IN_1		:in		std_logic;\r
	INT_IN_2		:in		std_logic;\r
	INT_IN_3		:in		std_logic;\r
	INT_IN_4		:in		std_logic;\r
	INT_IN_5		:in		std_logic;\r
	INT_IN_6		:in		std_logic;\r
	INT_IN_7		:in		std_logic;\r
	TRDYn				:in 	std_logic;  -- event 1 after read of Interrupt status register (low active)\r
	READ_XX5_4	:in 	std_logic;	-- event 2 after read of Interrupt status register\r
	INT_RES			:in		std_logic_vector(7 downto 0); -- clear selected interrupts\r
	INT_MASKE		:in		std_logic_vector(7 downto 0);	-- interrupt mask register\r
	INT_REG			:out	std_logic_vector(7 downto 0); -- interrupt status register\r
	INTAn				:out	std_logic;	-- second interrupt line for PCI analyzer\r
	PCI_INTAn		:out	std_logic		-- PCI interrupt line \r
	);\r
\r
end entity INTERRUPT;\r
\r
architecture INTERRUPT_DESIGN of INTERRUPT is\r
\r
	signal	SIG_TAST_Q		:std_logic;\r
	signal	SIG_TAST_Qn		:std_logic;\r
\r
\r
	signal	SIG_INTA			:std_logic; \r
\r
	signal FF_A			:std_logic_vector(7 downto 0);\r
	signal FF_B			:std_logic_vector(7 downto 0);	\r
	signal SET 			:std_logic_vector(7 downto 0);	\r
\r
	signal  SIG_PROPAGATE_INT :std_logic;\r
	signal  SIG_PROPAGATE_INT_SECOND :std_logic;\r
	signal  REG :std_logic_vector(7 downto 0);\r
\r
begin\r
\r
\r
\r
\r
------------------------------------------------------\r
	process (PCI_CLOCK) \r
	begin \r
		if  (PCI_CLOCK'event and PCI_CLOCK ='1')  then  \r
\r
			SIG_TAST_Q		<= not (TAST_SETn and SIG_TAST_Qn);\r
			\r
			SIG_TAST_Qn		<= not (TAST_RESn and SIG_TAST_Q);\r
	\r
		end if;\r
	end process; 	\r
\r
------------------------------------------------------\r
\r
	process (PCI_CLOCK)\r
	begin\r
    if (PCI_RSTn = '0') then\r
					SET <= "00000000";\r
          FF_A	<= "00000000";\r
          FF_B	<= "00000000";\r
\r
		elsif(PCI_CLOCK'event	and	PCI_CLOCK	=	'1')	then\r
   		if(RESET = '1') then\r
						SET <= "00000000";\r
            FF_A	<= "00000000";\r
            FF_B	<= "00000000";\r
      else	\r
\r
			FF_A(0)	<=			INT_IN_0 ;  -- Receive FIFO Empty Flag\r
\r
			FF_A(1)	<=			INT_IN_1 ;  -- Send FIFO Half Full\r
			FF_A(2)	<=			INT_IN_2 ; \r
			FF_A(3)	<=			INT_IN_3 ; \r
\r
			FF_A(4)	<=			INT_IN_4 ; \r
\r
			FF_A(5)	<=			INT_IN_5 ; \r
			FF_A(6)	<=			INT_IN_6 ; \r
			FF_A(7)	<=			INT_IN_7 ; \r
\r
			FF_B	<= FF_A ;\r
\r
			SET <= FF_A AND not FF_B;\r
		end if;\r
		end if;\r
	end process;\r
\r
	process (PCI_CLOCK,PCI_RSTn)\r
	begin\r
		if (PCI_RSTn = '0') then\r
			REG <= "00000000";\r
\r
		elsif(PCI_CLOCK'event	and	PCI_CLOCK	=	'1')	then\r
				if(RESET = '1') then\r
					REG <= "00000000";\r
\r
    		elsif(SIG_TAST_Q = '1') then\r
      			REG <= "00000000" or SET;\r
\r
        elsif (TRDYn = '0' AND READ_XX5_4 = '1') then\r
            REG <= (REG AND NOT INT_RES) OR SET;\r
        else\r
            REG <= REG OR SET;\r
        end if;\r
    end if;\r
	end process;\r
\r
	SIG_PROPAGATE_INT <= SIG_TAST_Q \r
            OR (REG(0) AND INT_MASKE(0)) \r
            OR (REG(1) AND INT_MASKE(1))\r
            OR (REG(2) AND INT_MASKE(2))\r
            OR (REG(3) AND INT_MASKE(3))\r
            OR (REG(4) AND INT_MASKE(4))\r
            OR (REG(5) AND INT_MASKE(5))\r
            OR (REG(6) AND INT_MASKE(6))\r
            OR (REG(7) AND INT_MASKE(7));\r
\r
	process (PCI_CLOCK)\r
	begin\r
		if(PCI_CLOCK'event	and	PCI_CLOCK	=	'1')	then\r
   	SIG_PROPAGATE_INT_SECOND	<= not SIG_PROPAGATE_INT;\r
    end if;\r
  end process;\r
\r
\r
   	  INTAn	<= not SIG_PROPAGATE_INT_SECOND;\r
    	PCI_INTAn	<= '0'	when SIG_PROPAGATE_INT_SECOND = '0'	else	'Z';\r
\r
	INT_REG <= REG;\r
\r
end architecture INTERRUPT_DESIGN;\r
Commit	Line	Data
377c0242	1	-- J.STELZNER\r
	2	-- INFORMATIK-3 LABOR\r
	3	-- 23.08.2006\r
	4	-- File: INTERRUPT.VHD\r
	5	\r
	6	library ieee;\r
	7	use ieee.std_logic_1164.all;\r
	8	\r
	9	entity INTERRUPT is\r
	10	port\r
	11	(\r
	12	PCI_CLOCK :in std_logic;\r
	13	PCI_RSTn :in std_logic; -- PCI reset is asynchron (low active)\r
	14	RESET :in std_logic;\r
	15	TAST_SETn :in std_logic;\r
	16	TAST_RESn :in std_logic;\r
	17	INT_IN_0 :in std_logic;\r
	18	INT_IN_1 :in std_logic;\r
	19	INT_IN_2 :in std_logic;\r
	20	INT_IN_3 :in std_logic;\r
	21	INT_IN_4 :in std_logic;\r
	22	INT_IN_5 :in std_logic;\r
	23	INT_IN_6 :in std_logic;\r
	24	INT_IN_7 :in std_logic;\r
	25	TRDYn :in std_logic; -- event 1 after read of Interrupt status register (low active)\r
	26	READ_XX5_4 :in std_logic; -- event 2 after read of Interrupt status register\r
	27	INT_RES :in std_logic_vector(7 downto 0); -- clear selected interrupts\r
	28	INT_MASKE :in std_logic_vector(7 downto 0); -- interrupt mask register\r
	29	INT_REG :out std_logic_vector(7 downto 0); -- interrupt status register\r
	30	INTAn :out std_logic; -- second interrupt line for PCI analyzer\r
	31	PCI_INTAn :out std_logic -- PCI interrupt line \r
	32	);\r
	33	\r
	34	end entity INTERRUPT;\r
	35	\r
	36	architecture INTERRUPT_DESIGN of INTERRUPT is\r
	37	\r
	38	signal SIG_TAST_Q :std_logic;\r
	39	signal SIG_TAST_Qn :std_logic;\r
	40	\r
	41	\r
	42	signal SIG_INTA :std_logic; \r
	43	\r
	44	signal FF_A :std_logic_vector(7 downto 0);\r
	45	signal FF_B :std_logic_vector(7 downto 0); \r
	46	signal SET :std_logic_vector(7 downto 0); \r
	47	\r
	48	signal SIG_PROPAGATE_INT :std_logic;\r
	49	signal SIG_PROPAGATE_INT_SECOND :std_logic;\r
	50	signal REG :std_logic_vector(7 downto 0);\r
	51	\r
	52	begin\r
	53	\r
	54	\r
	55	\r
	56	\r
	57	------------------------------------------------------\r
	58	process (PCI_CLOCK) \r
	59	begin \r
	60	if (PCI_CLOCK'event and PCI_CLOCK ='1') then \r
	61	\r
	62	SIG_TAST_Q <= not (TAST_SETn and SIG_TAST_Qn);\r
	63	\r
	64	SIG_TAST_Qn <= not (TAST_RESn and SIG_TAST_Q);\r
65	\r
66	end if;\r
67	end process; \r
68	\r
69	------------------------------------------------------\r
70	\r
71	process (PCI_CLOCK)\r
72	begin\r
73	if (PCI_RSTn = '0') then\r
74	SET <= "00000000";\r
75	FF_A <= "00000000";\r
76	FF_B <= "00000000";\r
77	\r
78	elsif(PCI_CLOCK'event and PCI_CLOCK = '1') then\r
79	if(RESET = '1') then\r
80	SET <= "00000000";\r
81	FF_A <= "00000000";\r
82	FF_B <= "00000000";\r
83	else \r
84	\r
85	FF_A(0) <= INT_IN_0 ; -- Receive FIFO Empty Flag\r
86	\r
87	FF_A(1) <= INT_IN_1 ; -- Send FIFO Half Full\r
88	FF_A(2) <= INT_IN_2 ; \r
89	FF_A(3) <= INT_IN_3 ; \r
90	\r
91	FF_A(4) <= INT_IN_4 ; \r
92	\r
93	FF_A(5) <= INT_IN_5 ; \r
94	FF_A(6) <= INT_IN_6 ; \r
95	FF_A(7) <= INT_IN_7 ; \r
96	\r
97	FF_B <= FF_A ;\r
98	\r
99	SET <= FF_A AND not FF_B;\r
100	end if;\r
101	end if;\r
102	end process;\r
103	\r
104	process (PCI_CLOCK,PCI_RSTn)\r
105	begin\r
106	if (PCI_RSTn = '0') then\r
107	REG <= "00000000";\r
108	\r
109	elsif(PCI_CLOCK'event and PCI_CLOCK = '1') then\r
110	if(RESET = '1') then\r
111	REG <= "00000000";\r
112	\r
113	elsif(SIG_TAST_Q = '1') then\r
114	REG <= "00000000" or SET;\r
115	\r
116	elsif (TRDYn = '0' AND READ_XX5_4 = '1') then\r
117	REG <= (REG AND NOT INT_RES) OR SET;\r
118	else\r
119	REG <= REG OR SET;\r
120	end if;\r
121	end if;\r
122	end process;\r
123	\r
124	SIG_PROPAGATE_INT <= SIG_TAST_Q \r
125	OR (REG(0) AND INT_MASKE(0)) \r
126	OR (REG(1) AND INT_MASKE(1))\r
127	OR (REG(2) AND INT_MASKE(2))\r
128	OR (REG(3) AND INT_MASKE(3))\r
129	OR (REG(4) AND INT_MASKE(4))\r
130	OR (REG(5) AND INT_MASKE(5))\r
131	OR (REG(6) AND INT_MASKE(6))\r
132	OR (REG(7) AND INT_MASKE(7));\r
133	\r
134	process (PCI_CLOCK)\r
135	begin\r
136	if(PCI_CLOCK'event and PCI_CLOCK = '1') then\r
137	SIG_PROPAGATE_INT_SECOND <= not SIG_PROPAGATE_INT;\r
138	end if;\r
139	end process;\r
140	\r
141	\r
142	INTAn <= not SIG_PROPAGATE_INT_SECOND;\r
143	PCI_INTAn <= '0' when SIG_PROPAGATE_INT_SECOND = '0' else 'Z';\r
144	\r
145	INT_REG <= REG;\r
146	\r
147	end architecture INTERRUPT_DESIGN;\r