first import of dhwk.
[raggedstone] / dhwk / source / PAR_SER_CON.vhd
CommitLineData
377c0242 1-- $Id: PAR_SER_CON.vhd,v 1.1 2007-03-10 11:24:03 sithglan Exp $\r
2\r
3library ieee;\r
4use ieee.std_logic_1164.all;\r
5use ieee.std_logic_unsigned.all;\r
6\r
7entity PAR_SER_CON is\r
8 port\r
9 (\r
10 PCI_CLOCK :in std_logic; \r
11 RESET :in std_logic; \r
12 PSC_ENABLE :in std_logic; -- Parallel Serial Converter Enable\r
13 SYNC_S_FIFO_EFn :in std_logic; -- Empty Flag (low active)\r
14 SPC_RDY_IN :in std_logic; -- Ready to receive data\r
15 PAR_IN :in std_logic_vector(7 downto 0);\r
16 SER_OUT :out std_logic; -- Serial Output\r
17 S_FIFO_READn :out std_logic -- FIFO Read (low active)\r
18 ); \r
19end entity PAR_SER_CON ;\r
20\r
21architecture PAR_SER_CON_DESIGN of PAR_SER_CON is\r
22\r
23constant STATE_END :std_logic_vector(3 downto 0) := "0001";\r
24constant STATE_SEND :std_logic_vector(3 downto 0) := "0010";\r
25constant STATE_SEND_BIT_0 :std_logic_vector(3 downto 0) := "0011";\r
26constant STATE_SEND_BIT_1 :std_logic_vector(3 downto 0) := "0100";\r
27constant STATE_SEND_BIT_2 :std_logic_vector(3 downto 0) := "0101";\r
28constant STATE_SEND_BIT_3 :std_logic_vector(3 downto 0) := "0110";\r
29constant STATE_SEND_BIT_4 :std_logic_vector(3 downto 0) := "0111";\r
30constant STATE_SEND_BIT_5 :std_logic_vector(3 downto 0) := "1000";\r
31constant STATE_SEND_BIT_6 :std_logic_vector(3 downto 0) := "1001";\r
32constant STATE_SEND_BIT_7 :std_logic_vector(3 downto 0) := "1010";\r
33\r
34signal COUNT :std_logic_vector (3 downto 0);\r
35signal STATE :std_logic_vector (3 downto 0); \r
36signal DATUM :std_logic_vector (7 downto 0);\r
37signal SYNC :std_logic; -- make SPC_RDY_IN stable\r
38\r
39attribute syn_state_machine:boolean;\r
40attribute syn_state_machine of STATE: signal is false;\r
41attribute syn_state_machine of COUNT: signal is false;\r
42begin\r
43\r
44process(PCI_CLOCK)\r
45begin\r
46 if (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
47 if ("0000" < COUNT) then\r
48 COUNT <= COUNT - 1;\r
49 end if;\r
50\r
51 if (RESET = '1') then\r
52 STATE <= STATE_SEND;\r
53 COUNT <= "0000";\r
54 SER_OUT <= '0';\r
55 S_FIFO_READn <= '1';\r
56\r
57 elsif (PSC_ENABLE = '1') then\r
58 if (COUNT = "0000") then\r
59 COUNT <= "0011";\r
60 case STATE is\r
61 when STATE_SEND =>\r
62 if(SYNC = '1' and SYNC_S_FIFO_EFn = '1') then\r
63 SER_OUT <= '1';\r
64 S_FIFO_READn <= '0';\r
65 STATE <= STATE_SEND_BIT_0;\r
66 end if;\r
67\r
68 when STATE_SEND_BIT_0 =>\r
69 DATUM <= PAR_IN;\r
70 S_FIFO_READn <= '1';\r
71 SER_OUT <= PAR_IN(0); \r
72 STATE <= STATE_SEND_BIT_1;\r
73 \r
74 when STATE_SEND_BIT_1 =>\r
75 SER_OUT <= DATUM(1); \r
76 STATE <= STATE_SEND_BIT_2;\r
77\r
78 when STATE_SEND_BIT_2 =>\r
79 SER_OUT <= DATUM(2); \r
80 STATE <= STATE_SEND_BIT_3;\r
81\r
82 when STATE_SEND_BIT_3 =>\r
83 SER_OUT <= DATUM(3); \r
84 STATE <= STATE_SEND_BIT_4;\r
85\r
86 when STATE_SEND_BIT_4 =>\r
87 SER_OUT <= DATUM(4); \r
88 STATE <= STATE_SEND_BIT_5;\r
89 \r
90 when STATE_SEND_BIT_5 =>\r
91 SER_OUT <= DATUM(5); \r
92 STATE <= STATE_SEND_BIT_6;\r
93\r
94 when STATE_SEND_BIT_6 =>\r
95 SER_OUT <= DATUM(6); \r
96 STATE <= STATE_SEND_BIT_7;\r
97 \r
98 when STATE_SEND_BIT_7 =>\r
99 SER_OUT <= DATUM(7); \r
100 STATE <= STATE_END;\r
101\r
102 when STATE_END =>\r
103 SER_OUT <= '0';\r
104 STATE <= STATE_SEND;\r
105\r
106 when others => STATE <= STATE_END;\r
107 end case;\r
108 end if; -- COUNT\r
109 end if; -- RESET ... / PSC_ENABLE ...\r
110 end if; -- PCI_CLOCK ...\r
111end process;\r
112\r
113process(PCI_CLOCK)\r
114begin\r
115 if (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
116 SYNC <= SPC_RDY_IN;\r
117 end if;\r
118end process;\r
119\r
120\r
121end architecture PAR_SER_CON_DESIGN;\r
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