[raggedstone] / dhwk / source / top.vhd

-- VHDL model created from schematic top.sch -- Jan 09 20:54:18 2007\r
\r
\r
\r
LIBRARY ieee;\r
\r
USE ieee.std_logic_1164.ALL;\r
USE ieee.numeric_std.ALL;\r
\r
\r
entity TOP is\r
      Port ( KONST_1 : In    std_logic;\r
             PCI_CBEn : In    std_logic_vector (3 downto 0);\r
             PCI_CLOCK : In    std_logic;\r
             PCI_FRAMEn : In    std_logic;\r
             PCI_IDSEL : In    std_logic;\r
             PCI_IRDYn : In    std_logic;\r
             PCI_RSTn : In    std_logic;\r
               R_EFn : In    std_logic;\r
               R_FFn : In    std_logic;\r
             R_FIFO_Q_OUT : In    std_logic_vector (7 downto 0);\r
               R_HFn : In    std_logic;\r
               S_EFn : In    std_logic;\r
               S_FFn : In    std_logic;\r
             S_FIFO_Q_OUT : In    std_logic_vector (7 downto 0);\r
               S_HFn : In    std_logic;\r
             SERIAL_IN : In    std_logic;\r
             SPC_RDY_IN : In    std_logic;\r
             TAST_RESn : In    std_logic;\r
             TAST_SETn : In    std_logic;\r
              PCI_AD : InOut std_logic_vector (31 downto 0);\r
             PCI_PAR : InOut std_logic;\r
             PCI_DEVSELn : Out   std_logic;\r
             PCI_INTAn : Out   std_logic;\r
             PCI_PERRn : Out   std_logic;\r
             PCI_SERRn : Out   std_logic;\r
             PCI_STOPn : Out   std_logic;\r
             PCI_TRDYn : Out   std_logic;\r
             R_FIFO_D_IN : Out   std_logic_vector (7 downto 0);\r
             R_FIFO_READn : Out   std_logic;\r
             R_FIFO_RESETn : Out   std_logic;\r
             R_FIFO_RTn : Out   std_logic;\r
             R_FIFO_WRITEn : Out   std_logic;\r
             S_FIFO_D_IN : Out   std_logic_vector (7 downto 0);\r
             S_FIFO_READn : Out   std_logic;\r
             S_FIFO_RESETn : Out   std_logic;\r
             S_FIFO_RTn : Out   std_logic;\r
             S_FIFO_WRITEn : Out   std_logic;\r
             SERIAL_OUT : Out   std_logic;\r
             SPC_RDY_OUT : Out   std_logic;\r
             TB_IDSEL : Out   std_logic;\r
             TB_nDEVSEL : Out   std_logic;\r
             TB_nINTA : Out   std_logic );\r
end TOP;\r
\r
architecture SCHEMATIC of TOP is\r
\r
   SIGNAL gnd : std_logic := '0';\r
   SIGNAL vcc : std_logic := '1';\r
\r
   signal READ_XX7_6 : std_logic;\r
   signal  RESERVE : std_logic;\r
   signal SR_ERROR : std_logic;\r
   signal  R_ERROR : std_logic;\r
   signal  S_ERROR : std_logic;\r
   signal WRITE_XX3_2 : std_logic;\r
   signal WRITE_XX5_4 : std_logic;\r
   signal WRITE_XX7_6 : std_logic;\r
   signal READ_XX1_0 : std_logic;\r
   signal READ_XX3_2 : std_logic;\r
   signal    INTAn : std_logic;\r
   signal    TRDYn : std_logic;\r
   signal READ_XX5_4 : std_logic;\r
   signal  DEVSELn : std_logic;\r
   signal FIFO_RDn : std_logic;\r
   signal WRITE_XX1_0 : std_logic;\r
   signal REG_OUT_XX6 : std_logic_vector (7 downto 0);\r
   signal SYNC_FLAG : std_logic_vector (7 downto 0);\r
   signal  INT_REG : std_logic_vector (7 downto 0);\r
   signal REVISON_ID : std_logic_vector (7 downto 0);\r
   signal VENDOR_ID : std_logic_vector (15 downto 0);\r
   signal READ_SEL : std_logic_vector (1 downto 0);\r
   signal   AD_REG : std_logic_vector (31 downto 0);\r
   signal REG_OUT_XX7 : std_logic_vector (7 downto 0);\r
\r
   component MESS_1_TB\r
      Port ( DEVSELn : In    std_logic;\r
               INTAn : In    std_logic;\r
             KONST_1 : In    std_logic;\r
             PCI_IDSEL : In    std_logic;\r
             REG_OUT_XX7 : In    std_logic_vector (7 downto 0);\r
             TB_DEVSELn : Out   std_logic;\r
             TB_INTAn : Out   std_logic;\r
             TB_PCI_IDSEL : Out   std_logic );\r
   end component;\r
\r
   component VEN_REV_ID\r
      Port (  REV_ID : Out   std_logic_vector (7 downto 0);\r
              VEN_ID : Out   std_logic_vector (15 downto 0) );\r
   end component;\r
\r
   component INTERRUPT\r
      Port ( INT_IN_0 : In    std_logic;\r
             INT_IN_1 : In    std_logic;\r
             INT_IN_2 : In    std_logic;\r
             INT_IN_3 : In    std_logic;\r
             INT_IN_4 : In    std_logic;\r
             INT_IN_5 : In    std_logic;\r
             INT_IN_6 : In    std_logic;\r
             INT_IN_7 : In    std_logic;\r
             INT_MASKE : In    std_logic_vector (7 downto 0);\r
             INT_RES : In    std_logic_vector (7 downto 0);\r
             PCI_CLOCK : In    std_logic;\r
             PCI_RSTn : In    std_logic;\r
             READ_XX5_4 : In    std_logic;\r
               RESET : In    std_logic;\r
             TAST_RESn : In    std_logic;\r
             TAST_SETn : In    std_logic;\r
               TRDYn : In    std_logic;\r
             INT_REG : Out   std_logic_vector (7 downto 0);\r
               INTAn : Out   std_logic;\r
             PCI_INTAn : Out   std_logic );\r
   end component;\r
\r
   component FIFO_CONTROL\r
      Port ( FIFO_RDn : In    std_logic;\r
             FLAG_IN_0 : In    std_logic;\r
             FLAG_IN_4 : In    std_logic;\r
                HOLD : In    std_logic;\r
             KONST_1 : In    std_logic;\r
             PCI_CLOCK : In    std_logic;\r
             PSC_ENABLE : In    std_logic;\r
               R_EFn : In    std_logic;\r
               R_FFn : In    std_logic;\r
               R_HFn : In    std_logic;\r
               RESET : In    std_logic;\r
               S_EFn : In    std_logic;\r
               S_FFn : In    std_logic;\r
             S_FIFO_Q_OUT : In    std_logic_vector (7 downto 0);\r
               S_HFn : In    std_logic;\r
             SERIAL_IN : In    std_logic;\r
             SPC_ENABLE : In    std_logic;\r
             SPC_RDY_IN : In    std_logic;\r
             WRITE_XX1_0 : In    std_logic;\r
             R_ERROR : Out   std_logic;\r
             R_FIFO_D_IN : Out   std_logic_vector (7 downto 0);\r
             R_FIFO_READn : Out   std_logic;\r
             R_FIFO_RESETn : Out   std_logic;\r
             R_FIFO_RETRANSMITn : Out   std_logic;\r
             R_FIFO_WRITEn : Out   std_logic;\r
             RESERVE : Out   std_logic;\r
             S_ERROR : Out   std_logic;\r
             S_FIFO_READn : Out   std_logic;\r
             S_FIFO_RESETn : Out   std_logic;\r
             S_FIFO_RETRANSMITn : Out   std_logic;\r
             S_FIFO_WRITEn : Out   std_logic;\r
             SERIAL_OUT : Out   std_logic;\r
             SPC_RDY_OUT : Out   std_logic;\r
             SR_ERROR : Out   std_logic;\r
             SYNC_FLAG : Out   std_logic_vector (7 downto 0) );\r
   end component;\r
\r
   component PCI_TOP\r
      Port (    FLAG : In    std_logic_vector (7 downto 0);\r
             INT_REG : In    std_logic_vector (7 downto 0);\r
             PCI_CBEn : In    std_logic_vector (3 downto 0);\r
             PCI_CLOCK : In    std_logic;\r
             PCI_FRAMEn : In    std_logic;\r
             PCI_IDSEL : In    std_logic;\r
             PCI_IRDYn : In    std_logic;\r
             PCI_RSTn : In    std_logic;\r
             R_FIFO_Q : In    std_logic_vector (7 downto 0);\r
             REVISON_ID : In    std_logic_vector (7 downto 0);\r
             VENDOR_ID : In    std_logic_vector (15 downto 0);\r
              PCI_AD : InOut std_logic_vector (31 downto 0);\r
             PCI_PAR : InOut std_logic;\r
              AD_REG : Out   std_logic_vector (31 downto 0);\r
             DEVSELn : Out   std_logic;\r
             FIFO_RDn : Out   std_logic;\r
             PCI_DEVSELn : Out   std_logic;\r
             PCI_PERRn : Out   std_logic;\r
             PCI_SERRn : Out   std_logic;\r
             PCI_STOPn : Out   std_logic;\r
             PCI_TRDYn : Out   std_logic;\r
             READ_SEL : Out   std_logic_vector (1 downto 0);\r
             READ_XX1_0 : Out   std_logic;\r
             READ_XX3_2 : Out   std_logic;\r
             READ_XX5_4 : Out   std_logic;\r
             READ_XX7_6 : Out   std_logic;\r
             REG_OUT_XX0 : Out   std_logic_vector (7 downto 0);\r
             REG_OUT_XX6 : Out   std_logic_vector (7 downto 0);\r
             REG_OUT_XX7 : Out   std_logic_vector (7 downto 0);\r
               TRDYn : Out   std_logic;\r
             WRITE_XX1_0 : Out   std_logic;\r
             WRITE_XX3_2 : Out   std_logic;\r
             WRITE_XX5_4 : Out   std_logic;\r
             WRITE_XX7_6 : Out   std_logic );\r
   end component;\r
\r
begin\r
\r
   I19 : MESS_1_TB\r
      Port Map ( DEVSELn=>DEVSELn, INTAn=>INTAn, KONST_1=>KONST_1,\r
                 PCI_IDSEL=>PCI_IDSEL,\r
                 REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7(7 downto 0),\r
                 TB_DEVSELn=>TB_nDEVSEL, TB_INTAn=>TB_nINTA,\r
                 TB_PCI_IDSEL=>TB_IDSEL );\r
   I18 : VEN_REV_ID\r
      Port Map ( REV_ID(7 downto 0)=>REVISON_ID(7 downto 0),\r
                 VEN_ID(15 downto 0)=>VENDOR_ID(15 downto 0) );\r
   I16 : INTERRUPT\r
      Port Map ( INT_IN_0=>SYNC_FLAG(1), INT_IN_1=>SYNC_FLAG(6),\r
                 INT_IN_2=>KONST_1, INT_IN_3=>KONST_1, INT_IN_4=>KONST_1,\r
                 INT_IN_5=>KONST_1, INT_IN_6=>KONST_1, INT_IN_7=>KONST_1,\r
                 INT_MASKE(7 downto 0)=>REG_OUT_XX6(7 downto 0),\r
                 INT_RES(7 downto 0)=>AD_REG(7 downto 0),\r
                 PCI_CLOCK=>PCI_CLOCK, PCI_RSTn=>PCI_RSTn,\r
                 READ_XX5_4=>READ_XX5_4, RESET=>REG_OUT_XX7(0),\r
                 TAST_RESn=>TAST_RESn, TAST_SETn=>TAST_SETn,\r
                 TRDYn=>TRDYn, INT_REG(7 downto 0)=>INT_REG(7 downto 0),\r
                 INTAn=>INTAn, PCI_INTAn=>PCI_INTAn );\r
   I14 : FIFO_CONTROL\r
      Port Map ( FIFO_RDn=>FIFO_RDn, FLAG_IN_0=>R_ERROR,\r
                 FLAG_IN_4=>S_ERROR, HOLD=>READ_SEL(0), KONST_1=>KONST_1,\r
                 PCI_CLOCK=>PCI_CLOCK, PSC_ENABLE=>REG_OUT_XX7(1),\r
                 R_EFn=>R_EFn, R_FFn=>R_FFn, R_HFn=>R_HFn,\r
                 RESET=>REG_OUT_XX7(0), S_EFn=>S_EFn, S_FFn=>S_FFn,\r
                 S_FIFO_Q_OUT(7 downto 0)=>S_FIFO_Q_OUT(7 downto 0),\r
                 S_HFn=>S_HFn, SERIAL_IN=>SERIAL_IN,\r
                 SPC_ENABLE=>REG_OUT_XX7(2), SPC_RDY_IN=>SPC_RDY_IN,\r
                 WRITE_XX1_0=>WRITE_XX1_0, R_ERROR=>R_ERROR,\r
                 R_FIFO_D_IN(7 downto 0)=>R_FIFO_D_IN(7 downto 0),\r
                 R_FIFO_READn=>R_FIFO_READn,\r
                 R_FIFO_RESETn=>R_FIFO_RESETn,\r
                 R_FIFO_RETRANSMITn=>R_FIFO_RTn,\r
                 R_FIFO_WRITEn=>R_FIFO_WRITEn, RESERVE=>RESERVE,\r
                 S_ERROR=>S_ERROR, S_FIFO_READn=>S_FIFO_READn,\r
                 S_FIFO_RESETn=>S_FIFO_RESETn,\r
                 S_FIFO_RETRANSMITn=>S_FIFO_RTn,\r
                 S_FIFO_WRITEn=>S_FIFO_WRITEn, SERIAL_OUT=>SERIAL_OUT,\r
                 SPC_RDY_OUT=>SPC_RDY_OUT, SR_ERROR=>SR_ERROR,\r
                 SYNC_FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0) );\r
   I1 : PCI_TOP\r
      Port Map ( FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0),\r
                 INT_REG(7 downto 0)=>INT_REG(7 downto 0),\r
                 PCI_CBEn(3 downto 0)=>PCI_CBEn(3 downto 0),\r
                 PCI_CLOCK=>PCI_CLOCK, PCI_FRAMEn=>PCI_FRAMEn,\r
                 PCI_IDSEL=>PCI_IDSEL, PCI_IRDYn=>PCI_IRDYn,\r
                 PCI_RSTn=>PCI_RSTn,\r
                 R_FIFO_Q(7 downto 0)=>R_FIFO_Q_OUT(7 downto 0),\r
                 REVISON_ID(7 downto 0)=>REVISON_ID(7 downto 0),\r
                 VENDOR_ID(15 downto 0)=>VENDOR_ID(15 downto 0),\r
                 PCI_AD(31 downto 0)=>PCI_AD(31 downto 0),\r
                 PCI_PAR=>PCI_PAR,\r
                 AD_REG(31 downto 0)=>AD_REG(31 downto 0),\r
                 DEVSELn=>DEVSELn, FIFO_RDn=>FIFO_RDn,\r
                 PCI_DEVSELn=>PCI_DEVSELn, PCI_PERRn=>PCI_PERRn,\r
                 PCI_SERRn=>PCI_SERRn, PCI_STOPn=>PCI_STOPn,\r
                 PCI_TRDYn=>PCI_TRDYn,\r
                 READ_SEL(1 downto 0)=>READ_SEL(1 downto 0),\r
                 READ_XX1_0=>READ_XX1_0, READ_XX3_2=>READ_XX3_2,\r
                 READ_XX5_4=>READ_XX5_4, READ_XX7_6=>READ_XX7_6,\r
                 REG_OUT_XX0(7 downto 0)=>S_FIFO_D_IN(7 downto 0),\r
                 REG_OUT_XX6(7 downto 0)=>REG_OUT_XX6(7 downto 0),\r
                 REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7(7 downto 0),\r
                 TRDYn=>TRDYn, WRITE_XX1_0=>WRITE_XX1_0,\r
                 WRITE_XX3_2=>WRITE_XX3_2, WRITE_XX5_4=>WRITE_XX5_4,\r
                 WRITE_XX7_6=>WRITE_XX7_6 );\r
\r
end SCHEMATIC;\r
Commit	Line	Data
377c0242	1	-- VHDL model created from schematic top.sch -- Jan 09 20:54:18 2007\r
	2	\r
	3	\r
	4	\r
	5	LIBRARY ieee;\r
	6	\r
	7	USE ieee.std_logic_1164.ALL;\r
	8	USE ieee.numeric_std.ALL;\r
	9	\r
	10	\r
	11	entity TOP is\r
	12	Port ( KONST_1 : In std_logic;\r
	13	PCI_CBEn : In std_logic_vector (3 downto 0);\r
	14	PCI_CLOCK : In std_logic;\r
	15	PCI_FRAMEn : In std_logic;\r
	16	PCI_IDSEL : In std_logic;\r
	17	PCI_IRDYn : In std_logic;\r
	18	PCI_RSTn : In std_logic;\r
	19	R_EFn : In std_logic;\r
	20	R_FFn : In std_logic;\r
	21	R_FIFO_Q_OUT : In std_logic_vector (7 downto 0);\r
	22	R_HFn : In std_logic;\r
	23	S_EFn : In std_logic;\r
	24	S_FFn : In std_logic;\r
	25	S_FIFO_Q_OUT : In std_logic_vector (7 downto 0);\r
	26	S_HFn : In std_logic;\r
	27	SERIAL_IN : In std_logic;\r
	28	SPC_RDY_IN : In std_logic;\r
	29	TAST_RESn : In std_logic;\r
	30	TAST_SETn : In std_logic;\r
	31	PCI_AD : InOut std_logic_vector (31 downto 0);\r
	32	PCI_PAR : InOut std_logic;\r
	33	PCI_DEVSELn : Out std_logic;\r
	34	PCI_INTAn : Out std_logic;\r
	35	PCI_PERRn : Out std_logic;\r
	36	PCI_SERRn : Out std_logic;\r
	37	PCI_STOPn : Out std_logic;\r
	38	PCI_TRDYn : Out std_logic;\r
	39	R_FIFO_D_IN : Out std_logic_vector (7 downto 0);\r
	40	R_FIFO_READn : Out std_logic;\r
	41	R_FIFO_RESETn : Out std_logic;\r
	42	R_FIFO_RTn : Out std_logic;\r
	43	R_FIFO_WRITEn : Out std_logic;\r
	44	S_FIFO_D_IN : Out std_logic_vector (7 downto 0);\r
	45	S_FIFO_READn : Out std_logic;\r
	46	S_FIFO_RESETn : Out std_logic;\r
	47	S_FIFO_RTn : Out std_logic;\r
	48	S_FIFO_WRITEn : Out std_logic;\r
	49	SERIAL_OUT : Out std_logic;\r
	50	SPC_RDY_OUT : Out std_logic;\r
	51	TB_IDSEL : Out std_logic;\r
	52	TB_nDEVSEL : Out std_logic;\r
	53	TB_nINTA : Out std_logic );\r
	54	end TOP;\r
	55	\r
	56	architecture SCHEMATIC of TOP is\r
	57	\r
	58	SIGNAL gnd : std_logic := '0';\r
	59	SIGNAL vcc : std_logic := '1';\r
	60	\r
	61	signal READ_XX7_6 : std_logic;\r
	62	signal RESERVE : std_logic;\r
	63	signal SR_ERROR : std_logic;\r
	64	signal R_ERROR : std_logic;\r
65	signal S_ERROR : std_logic;\r
66	signal WRITE_XX3_2 : std_logic;\r
67	signal WRITE_XX5_4 : std_logic;\r
68	signal WRITE_XX7_6 : std_logic;\r
69	signal READ_XX1_0 : std_logic;\r
70	signal READ_XX3_2 : std_logic;\r
71	signal INTAn : std_logic;\r
72	signal TRDYn : std_logic;\r
73	signal READ_XX5_4 : std_logic;\r
74	signal DEVSELn : std_logic;\r
75	signal FIFO_RDn : std_logic;\r
76	signal WRITE_XX1_0 : std_logic;\r
77	signal REG_OUT_XX6 : std_logic_vector (7 downto 0);\r
78	signal SYNC_FLAG : std_logic_vector (7 downto 0);\r
79	signal INT_REG : std_logic_vector (7 downto 0);\r
80	signal REVISON_ID : std_logic_vector (7 downto 0);\r
81	signal VENDOR_ID : std_logic_vector (15 downto 0);\r
82	signal READ_SEL : std_logic_vector (1 downto 0);\r
83	signal AD_REG : std_logic_vector (31 downto 0);\r
84	signal REG_OUT_XX7 : std_logic_vector (7 downto 0);\r
85	\r
86	component MESS_1_TB\r
87	Port ( DEVSELn : In std_logic;\r
88	INTAn : In std_logic;\r
89	KONST_1 : In std_logic;\r
90	PCI_IDSEL : In std_logic;\r
91	REG_OUT_XX7 : In std_logic_vector (7 downto 0);\r
92	TB_DEVSELn : Out std_logic;\r
93	TB_INTAn : Out std_logic;\r
94	TB_PCI_IDSEL : Out std_logic );\r
95	end component;\r
96	\r
97	component VEN_REV_ID\r
98	Port ( REV_ID : Out std_logic_vector (7 downto 0);\r
99	VEN_ID : Out std_logic_vector (15 downto 0) );\r
100	end component;\r
101	\r
102	component INTERRUPT\r
103	Port ( INT_IN_0 : In std_logic;\r
104	INT_IN_1 : In std_logic;\r
105	INT_IN_2 : In std_logic;\r
106	INT_IN_3 : In std_logic;\r
107	INT_IN_4 : In std_logic;\r
108	INT_IN_5 : In std_logic;\r
109	INT_IN_6 : In std_logic;\r
110	INT_IN_7 : In std_logic;\r
111	INT_MASKE : In std_logic_vector (7 downto 0);\r
112	INT_RES : In std_logic_vector (7 downto 0);\r
113	PCI_CLOCK : In std_logic;\r
114	PCI_RSTn : In std_logic;\r
115	READ_XX5_4 : In std_logic;\r
116	RESET : In std_logic;\r
117	TAST_RESn : In std_logic;\r
118	TAST_SETn : In std_logic;\r
119	TRDYn : In std_logic;\r
120	INT_REG : Out std_logic_vector (7 downto 0);\r
121	INTAn : Out std_logic;\r
122	PCI_INTAn : Out std_logic );\r
123	end component;\r
124	\r
125	component FIFO_CONTROL\r
126	Port ( FIFO_RDn : In std_logic;\r
127	FLAG_IN_0 : In std_logic;\r
128	FLAG_IN_4 : In std_logic;\r
129	HOLD : In std_logic;\r
130	KONST_1 : In std_logic;\r
131	PCI_CLOCK : In std_logic;\r
132	PSC_ENABLE : In std_logic;\r
133	R_EFn : In std_logic;\r
134	R_FFn : In std_logic;\r
135	R_HFn : In std_logic;\r
136	RESET : In std_logic;\r
137	S_EFn : In std_logic;\r
138	S_FFn : In std_logic;\r
139	S_FIFO_Q_OUT : In std_logic_vector (7 downto 0);\r
140	S_HFn : In std_logic;\r
141	SERIAL_IN : In std_logic;\r
142	SPC_ENABLE : In std_logic;\r
143	SPC_RDY_IN : In std_logic;\r
144	WRITE_XX1_0 : In std_logic;\r
145	R_ERROR : Out std_logic;\r
146	R_FIFO_D_IN : Out std_logic_vector (7 downto 0);\r
147	R_FIFO_READn : Out std_logic;\r
148	R_FIFO_RESETn : Out std_logic;\r
149	R_FIFO_RETRANSMITn : Out std_logic;\r
150	R_FIFO_WRITEn : Out std_logic;\r
151	RESERVE : Out std_logic;\r
152	S_ERROR : Out std_logic;\r
153	S_FIFO_READn : Out std_logic;\r
154	S_FIFO_RESETn : Out std_logic;\r
155	S_FIFO_RETRANSMITn : Out std_logic;\r
156	S_FIFO_WRITEn : Out std_logic;\r
157	SERIAL_OUT : Out std_logic;\r
158	SPC_RDY_OUT : Out std_logic;\r
159	SR_ERROR : Out std_logic;\r
160	SYNC_FLAG : Out std_logic_vector (7 downto 0) );\r
161	end component;\r
162	\r
163	component PCI_TOP\r
164	Port ( FLAG : In std_logic_vector (7 downto 0);\r
165	INT_REG : In std_logic_vector (7 downto 0);\r
166	PCI_CBEn : In std_logic_vector (3 downto 0);\r
167	PCI_CLOCK : In std_logic;\r
168	PCI_FRAMEn : In std_logic;\r
169	PCI_IDSEL : In std_logic;\r
170	PCI_IRDYn : In std_logic;\r
171	PCI_RSTn : In std_logic;\r
172	R_FIFO_Q : In std_logic_vector (7 downto 0);\r
173	REVISON_ID : In std_logic_vector (7 downto 0);\r
174	VENDOR_ID : In std_logic_vector (15 downto 0);\r
175	PCI_AD : InOut std_logic_vector (31 downto 0);\r
176	PCI_PAR : InOut std_logic;\r
177	AD_REG : Out std_logic_vector (31 downto 0);\r
178	DEVSELn : Out std_logic;\r
179	FIFO_RDn : Out std_logic;\r
180	PCI_DEVSELn : Out std_logic;\r
181	PCI_PERRn : Out std_logic;\r
182	PCI_SERRn : Out std_logic;\r
183	PCI_STOPn : Out std_logic;\r
184	PCI_TRDYn : Out std_logic;\r
185	READ_SEL : Out std_logic_vector (1 downto 0);\r
186	READ_XX1_0 : Out std_logic;\r
187	READ_XX3_2 : Out std_logic;\r
188	READ_XX5_4 : Out std_logic;\r
189	READ_XX7_6 : Out std_logic;\r
190	REG_OUT_XX0 : Out std_logic_vector (7 downto 0);\r
191	REG_OUT_XX6 : Out std_logic_vector (7 downto 0);\r
192	REG_OUT_XX7 : Out std_logic_vector (7 downto 0);\r
193	TRDYn : Out std_logic;\r
194	WRITE_XX1_0 : Out std_logic;\r
195	WRITE_XX3_2 : Out std_logic;\r
196	WRITE_XX5_4 : Out std_logic;\r
197	WRITE_XX7_6 : Out std_logic );\r
198	end component;\r
199	\r
200	begin\r
201	\r
202	I19 : MESS_1_TB\r
203	Port Map ( DEVSELn=>DEVSELn, INTAn=>INTAn, KONST_1=>KONST_1,\r
204	PCI_IDSEL=>PCI_IDSEL,\r
205	REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7(7 downto 0),\r
206	TB_DEVSELn=>TB_nDEVSEL, TB_INTAn=>TB_nINTA,\r
207	TB_PCI_IDSEL=>TB_IDSEL );\r
208	I18 : VEN_REV_ID\r
209	Port Map ( REV_ID(7 downto 0)=>REVISON_ID(7 downto 0),\r
210	VEN_ID(15 downto 0)=>VENDOR_ID(15 downto 0) );\r
211	I16 : INTERRUPT\r
212	Port Map ( INT_IN_0=>SYNC_FLAG(1), INT_IN_1=>SYNC_FLAG(6),\r
213	INT_IN_2=>KONST_1, INT_IN_3=>KONST_1, INT_IN_4=>KONST_1,\r
214	INT_IN_5=>KONST_1, INT_IN_6=>KONST_1, INT_IN_7=>KONST_1,\r
215	INT_MASKE(7 downto 0)=>REG_OUT_XX6(7 downto 0),\r
216	INT_RES(7 downto 0)=>AD_REG(7 downto 0),\r
217	PCI_CLOCK=>PCI_CLOCK, PCI_RSTn=>PCI_RSTn,\r
218	READ_XX5_4=>READ_XX5_4, RESET=>REG_OUT_XX7(0),\r
219	TAST_RESn=>TAST_RESn, TAST_SETn=>TAST_SETn,\r
220	TRDYn=>TRDYn, INT_REG(7 downto 0)=>INT_REG(7 downto 0),\r
221	INTAn=>INTAn, PCI_INTAn=>PCI_INTAn );\r
222	I14 : FIFO_CONTROL\r
223	Port Map ( FIFO_RDn=>FIFO_RDn, FLAG_IN_0=>R_ERROR,\r
224	FLAG_IN_4=>S_ERROR, HOLD=>READ_SEL(0), KONST_1=>KONST_1,\r
225	PCI_CLOCK=>PCI_CLOCK, PSC_ENABLE=>REG_OUT_XX7(1),\r
226	R_EFn=>R_EFn, R_FFn=>R_FFn, R_HFn=>R_HFn,\r
227	RESET=>REG_OUT_XX7(0), S_EFn=>S_EFn, S_FFn=>S_FFn,\r
228	S_FIFO_Q_OUT(7 downto 0)=>S_FIFO_Q_OUT(7 downto 0),\r
229	S_HFn=>S_HFn, SERIAL_IN=>SERIAL_IN,\r
230	SPC_ENABLE=>REG_OUT_XX7(2), SPC_RDY_IN=>SPC_RDY_IN,\r
231	WRITE_XX1_0=>WRITE_XX1_0, R_ERROR=>R_ERROR,\r
232	R_FIFO_D_IN(7 downto 0)=>R_FIFO_D_IN(7 downto 0),\r
233	R_FIFO_READn=>R_FIFO_READn,\r
234	R_FIFO_RESETn=>R_FIFO_RESETn,\r
235	R_FIFO_RETRANSMITn=>R_FIFO_RTn,\r
236	R_FIFO_WRITEn=>R_FIFO_WRITEn, RESERVE=>RESERVE,\r
237	S_ERROR=>S_ERROR, S_FIFO_READn=>S_FIFO_READn,\r
238	S_FIFO_RESETn=>S_FIFO_RESETn,\r
239	S_FIFO_RETRANSMITn=>S_FIFO_RTn,\r
240	S_FIFO_WRITEn=>S_FIFO_WRITEn, SERIAL_OUT=>SERIAL_OUT,\r
241	SPC_RDY_OUT=>SPC_RDY_OUT, SR_ERROR=>SR_ERROR,\r
242	SYNC_FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0) );\r
243	I1 : PCI_TOP\r
244	Port Map ( FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0),\r
245	INT_REG(7 downto 0)=>INT_REG(7 downto 0),\r
246	PCI_CBEn(3 downto 0)=>PCI_CBEn(3 downto 0),\r
247	PCI_CLOCK=>PCI_CLOCK, PCI_FRAMEn=>PCI_FRAMEn,\r
248	PCI_IDSEL=>PCI_IDSEL, PCI_IRDYn=>PCI_IRDYn,\r
249	PCI_RSTn=>PCI_RSTn,\r
250	R_FIFO_Q(7 downto 0)=>R_FIFO_Q_OUT(7 downto 0),\r
251	REVISON_ID(7 downto 0)=>REVISON_ID(7 downto 0),\r
252	VENDOR_ID(15 downto 0)=>VENDOR_ID(15 downto 0),\r
253	PCI_AD(31 downto 0)=>PCI_AD(31 downto 0),\r
254	PCI_PAR=>PCI_PAR,\r
255	AD_REG(31 downto 0)=>AD_REG(31 downto 0),\r
256	DEVSELn=>DEVSELn, FIFO_RDn=>FIFO_RDn,\r
257	PCI_DEVSELn=>PCI_DEVSELn, PCI_PERRn=>PCI_PERRn,\r
258	PCI_SERRn=>PCI_SERRn, PCI_STOPn=>PCI_STOPn,\r
259	PCI_TRDYn=>PCI_TRDYn,\r
260	READ_SEL(1 downto 0)=>READ_SEL(1 downto 0),\r
261	READ_XX1_0=>READ_XX1_0, READ_XX3_2=>READ_XX3_2,\r
262	READ_XX5_4=>READ_XX5_4, READ_XX7_6=>READ_XX7_6,\r
263	REG_OUT_XX0(7 downto 0)=>S_FIFO_D_IN(7 downto 0),\r
264	REG_OUT_XX6(7 downto 0)=>REG_OUT_XX6(7 downto 0),\r
265	REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7(7 downto 0),\r
266	TRDYn=>TRDYn, WRITE_XX1_0=>WRITE_XX1_0,\r
267	WRITE_XX3_2=>WRITE_XX3_2, WRITE_XX5_4=>WRITE_XX5_4,\r
268	WRITE_XX7_6=>WRITE_XX7_6 );\r
269	\r
270	end SCHEMATIC;\r