name ports
[raggedstone] / dhwk / source / Addr_regi.vhd
CommitLineData
377c0242 1-- J.STELZNER\r
2-- INFORMATIK-3 LABOR\r
3-- 23.08.2006\r
4-- File: ADDR_REG.VHD\r
5\r
6library IEEE;\r
7use IEEE.std_logic_1164.all;\r
8\r
9entity ADDR_REGI is\r
10 port\r
11 (\r
12 PCI_CLOCK :in std_logic;\r
13 PCI_RSTn :in std_logic;\r
14 LOAD_ADDR_REG :in std_logic;\r
15 AD_REG :in std_logic_vector (31 downto 0);\r
16 ADDR_REG :out std_logic_vector (31 downto 0)\r
17 );\r
18end entity ADDR_REGI;\r
19\r
20architecture ADDR_REGI_DESIGN of ADDR_REGI is\r
21\r
22 signal REG_ADDR :std_logic_vector (31 downto 0); \r
23\r
24begin \r
25\r
26 process (PCI_CLOCK, PCI_RSTn) \r
27 begin\r
28 if PCI_RSTn = '0' then REG_ADDR <= X"00000000";\r
29\r
30 elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
31\r
32 if LOAD_ADDR_REG = '1' then\r
33 REG_ADDR <= AD_REG;\r
34\r
35 else REG_ADDR <= REG_ADDR;\r
36 end if;\r
37\r
38 end if;\r
39 end process;\r
40\r
41 ADDR_REG <= REG_ADDR;\r
42\r
43end architecture ADDR_REGI_DESIGN;\r
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