[raggedstone] / ethernet / source / top.vhd

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

entity ethernet is
PORT(
        PCI_AD : INOUT std_logic_vector(31 downto 0);
        PCI_CLOCK : IN std_logic;
        PCI_IDSEL : IN std_logic;
        PCI_CBEn : INOUT std_logic_vector (3 downto 0);
        PCI_FRAMEn : INOUT std_logic;
        PCI_IRDYn : INOUT std_logic;
        PCI_RSTn : INOUT std_logic;
        PCI_DEVSELn : INOUT std_logic;
        PCI_INTAn : INOUT std_logic;
        PCI_PERRn : INOUT std_logic;
        PCI_SERRn : INOUT std_logic;
        PCI_STOPn : INOUT std_logic;
        PCI_TRDYn : INOUT std_logic;
        PCI_PAR   : INOUT std_logic;
        PCI_REQn  : OUT std_logic;
        PCI_GNTn : IN std_logic;

        MTX_CLK_PAD_I : IN std_logic;
        MTXD_PAD_O : OUT std_logic_vector (3 downto 0);
        MTXEN_PAD_O : OUT std_logic;
        MRX_CLK_PAD_I : IN std_logic;
        MRXD_PAD_I : IN std_logic_vector (3 downto 0);
        MRXDV_PAD_I : IN std_logic;
        MRXERR_PAD_I : IN std_logic;
        MCOLL_PAD_I : IN std_logic;
        MCRS_PAD_I : IN std_logic;
        MD_PAD_IO : INOUT std_logic;
        MDC_PAD_O : OUT std_logic;

	LED_2 : OUT std_logic
);
end ethernet;

architecture ethernet_arch of ethernet is

COMPONENT eth_top
PORT(
        wb_clk_i : IN std_logic;
        wb_rst_i : IN std_logic;
        wb_dat_i : IN std_logic_vector(31 downto 0);
        wb_adr_i : IN std_logic_vector(11 downto 2);
        wb_sel_i : IN std_logic_vector(3 downto 0);
        wb_we_i : IN std_logic;
        wb_cyc_i : IN std_logic;
        wb_stb_i : IN std_logic;
        m_wb_dat_i : IN std_logic_vector(31 downto 0);
        m_wb_ack_i : IN std_logic;
        m_wb_err_i : IN std_logic;
        mtx_clk_pad_i : IN std_logic;
        mrx_clk_pad_i : IN std_logic;
        mrxd_pad_i : IN std_logic_vector(3 downto 0);
        mrxdv_pad_i : IN std_logic;
        mrxerr_pad_i : IN std_logic;
        mcoll_pad_i : IN std_logic;
        mcrs_pad_i : IN std_logic;
        md_pad_i : IN std_logic;          
        wb_dat_o : OUT std_logic_vector(31 downto 0);
        wb_ack_o : OUT std_logic;
        wb_err_o : OUT std_logic;
        m_wb_adr_o : OUT std_logic_vector(31 downto 0);
        m_wb_sel_o : OUT std_logic_vector(3 downto 0);
        m_wb_we_o : OUT std_logic;
        m_wb_dat_o : OUT std_logic_vector(31 downto 0);
        m_wb_cyc_o : OUT std_logic;
        m_wb_stb_o : OUT std_logic;
        mtxd_pad_o : OUT std_logic_vector(3 downto 0);
        mtxen_pad_o : OUT std_logic;
        mtxerr_pad_o : OUT std_logic;
        mdc_pad_o : OUT std_logic;
        md_pad_o : OUT std_logic;
        md_padoe_o : OUT std_logic;
        m_wb_cti_o : OUT std_logic_vector(2 downto 0);
        m_wb_bte_o : OUT std_logic_vector(1 downto 0);
        int_o : OUT std_logic
        );
END COMPONENT;

COMPONENT pci_bridge32
PORT(
        wb_clk_i : IN std_logic;
        wb_rst_i : IN std_logic;
        wb_int_i : IN std_logic;
        wbs_adr_i : IN std_logic_vector(31 downto 0);
        wbs_dat_i : IN std_logic_vector(31 downto 0);
        wbs_sel_i : IN std_logic_vector(3 downto 0);
        wbs_cyc_i : IN std_logic;
        wbs_stb_i : IN std_logic;
        wbs_we_i : IN std_logic;
        wbs_cti_i : IN std_logic_vector(2 downto 0);
        wbs_bte_i : IN std_logic_vector(1 downto 0);
        wbm_dat_i : IN std_logic_vector(31 downto 0);
        wbm_ack_i : IN std_logic;
        wbm_rty_i : IN std_logic;
        wbm_err_i : IN std_logic;
        pci_clk_i : IN std_logic;
        pci_rst_i : IN std_logic;
        pci_inta_i : IN std_logic;
        pci_gnt_i : IN std_logic;
        pci_frame_i : IN std_logic;
        pci_irdy_i : IN std_logic;
        pci_idsel_i : IN std_logic;
        pci_devsel_i : IN std_logic;
        pci_trdy_i : IN std_logic;
        pci_stop_i : IN std_logic;
        pci_ad_i : IN std_logic_vector(31 downto 0);
        pci_cbe_i : IN std_logic_vector(3 downto 0);
        pci_par_i : IN std_logic;
        pci_perr_i : IN std_logic;          
        wb_rst_o : OUT std_logic;
        wb_int_o : OUT std_logic;
        wbs_dat_o : OUT std_logic_vector(31 downto 0);
        wbs_ack_o : OUT std_logic;
        wbs_rty_o : OUT std_logic;
        wbs_err_o : OUT std_logic;
        wbm_adr_o : OUT std_logic_vector(31 downto 0);
        wbm_dat_o : OUT std_logic_vector(31 downto 0);
        wbm_sel_o : OUT std_logic_vector(3 downto 0);
        wbm_cyc_o : OUT std_logic;
        wbm_stb_o : OUT std_logic;
        wbm_we_o : OUT std_logic;
        wbm_cti_o : OUT std_logic_vector(2 downto 0);
        wbm_bte_o : OUT std_logic_vector(1 downto 0);
        pci_rst_o : OUT std_logic;
        pci_inta_o : OUT std_logic;
        pci_rst_oe_o : OUT std_logic;
        pci_inta_oe_o : OUT std_logic;
        pci_req_o : OUT std_logic;
        pci_req_oe_o : OUT std_logic;
        pci_frame_o : OUT std_logic;
        pci_frame_oe_o : OUT std_logic;
        pci_irdy_oe_o : OUT std_logic;
        pci_devsel_oe_o : OUT std_logic;
        pci_trdy_oe_o : OUT std_logic;
        pci_stop_oe_o : OUT std_logic;
        pci_ad_oe_o : OUT std_logic_vector(31 downto 0);
        pci_cbe_oe_o : OUT std_logic_vector(3 downto 0);
        pci_irdy_o : OUT std_logic;
        pci_devsel_o : OUT std_logic;
        pci_trdy_o : OUT std_logic;
        pci_stop_o : OUT std_logic;
        pci_ad_o : OUT std_logic_vector(31 downto 0);
        pci_cbe_o : OUT std_logic_vector(3 downto 0);
        pci_par_o : OUT std_logic;
        pci_par_oe_o : OUT std_logic;
        pci_perr_o : OUT std_logic;
        pci_perr_oe_o : OUT std_logic;
        pci_serr_o : OUT std_logic;
        pci_serr_oe_o : OUT std_logic
        );
END COMPONENT;

component icon
port (
	control0 : out std_logic_vector(35 downto 0)
	);
end component;

component ila
port (
	control : in std_logic_vector(35 downto 0);
	clk : in std_logic;
	data : in std_logic_vector(63 downto 0);
	trig0 : in std_logic_vector(31 downto 0)
	);
end component;

signal pci_rst_o : std_logic;
signal pci_rst_oe_o : std_logic;
signal pci_inta_o : std_logic;
signal pci_inta_oe_o : std_logic;
signal pci_req_o : std_logic;
signal pci_req_oe_o : std_logic;
signal pci_frame_o : std_logic;
signal pci_frame_oe_o : std_logic;
signal pci_irdy_o : std_logic;
signal pci_irdy_oe_o : std_logic;
signal pci_devsel_o : std_logic;
signal pci_devsel_oe_o : std_logic;
signal pci_trdy_o : std_logic;
signal pci_trdy_oe_o : std_logic;
signal pci_stop_o : std_logic;
signal pci_stop_oe_o : std_logic;
signal pci_par_o : std_logic;
signal pci_par_oe_o : std_logic;
signal pci_perr_o : std_logic;
signal pci_perr_oe_o : std_logic;
signal pci_serr_o : std_logic;
signal pci_serr_oe_o : std_logic;
signal pci_ad_oe_o : std_logic_vector(31 downto 0);
signal pci_cbe_oe_o : std_logic_vector(3 downto 0);
signal pci_ad_o : std_logic_vector (31 downto 0);
signal pci_cbe_o : std_logic_vector (3 downto 0);

signal wb_clk_i : std_logic;
signal wb_rst_i : std_logic;
signal wb_dat_i : std_logic_vector (31 downto 0);
signal wb_dat_o : std_logic_vector (31 downto 0);
signal wb_adr_i : std_logic_vector (11 downto 2);
signal wb_sel_i : std_logic_vector (3 downto 0);
signal wb_we_i : std_logic;
signal wb_cyc_i : std_logic;
signal wb_stb_i : std_logic;
signal wb_ack_o : std_logic;
signal wb_err_o : std_logic;
signal m_wb_adr_o : std_logic_vector(31 downto 0);
signal m_wb_sel_o : std_logic_vector(3 downto 0);
signal m_wb_we_o : std_logic;
signal m_wb_dat_o : std_logic_vector(31 downto 0);
signal m_wb_dat_i : std_logic_vector(31 downto 0);
signal m_wb_cyc_o : std_logic;
signal m_wb_stb_o : std_logic;
signal m_wb_ack_i : std_logic;
signal m_wb_err_i : std_logic;
signal md_pad_o : std_logic;
signal md_padoe_o : std_logic;
signal int_o : std_logic;
signal wbm_adr_o : std_logic_vector(31 downto 0);

signal m_wb_cti_o : std_logic_vector(2 downto 0);
signal m_wb_bte_o : std_logic_vector(1 downto 0);

signal control0 : std_logic_vector(35 downto 0);
signal data : std_logic_vector(63 downto 0);
signal trig0 : std_logic_vector(31 downto 0);


BEGIN

PCI_RSTn    <= pci_rst_o    when (pci_rst_oe_o = '1')     else 'Z';
PCI_INTAn   <= pci_inta_o   when (pci_inta_oe_o = '1')    else 'Z';
PCI_REQn    <= pci_req_o    when (pci_req_oe_o = '1')     else 'Z';
PCI_FRAMEn  <= pci_frame_o  when (pci_frame_oe_o = '1')     else 'Z';
PCI_IRDYn   <= pci_irdy_o   when (pci_irdy_oe_o = '1')    else 'Z';
PCI_DEVSELn <= pci_devsel_o when (pci_devsel_oe_o = '1')  else 'Z';
PCI_TRDYn   <= pci_trdy_o   when (pci_trdy_oe_o = '1')    else 'Z';
PCI_STOPn   <= pci_stop_o   when (pci_stop_oe_o = '1')    else 'Z';
PCI_PAR     <= pci_par_o    when (pci_par_oe_o = '1')     else 'Z';
PCI_PERRn   <= pci_perr_o   when (pci_perr_oe_o = '1')    else 'Z';
PCI_SERRn   <= pci_serr_o   when (pci_serr_oe_o = '1')    else 'Z';
MD_PAD_IO   <= md_pad_o     when (md_padoe_o = '1')       else 'Z';

BLA1: FOR i in 31 downto 0 generate
PCI_AD(i) <= pci_ad_o(i) when (pci_ad_oe_o(i) = '1') else 'Z';
end generate;

BLA2: FOR i in 3 downto 0 generate
PCI_CBEn(i) <= pci_cbe_o(i) when (pci_cbe_oe_o(i) = '1') else 'Z';
end generate;

wb_adr_i(11 downto 2) <= (others => '0');
wb_adr_i <= wbm_adr_o (7 downto 2);

wb_clk_i <= PCI_CLOCK;

data(31 downto 0)  <= wbm_adr_o;
data(40 downto 33) <= wbm_adr_o (7 downto 0);
data(63 downto 41) <= (others => '0');

trig0(31 downto 0) <= (
	0 => wb_stb_i,
	others => '0'
);

Inst_pci_bridge32: pci_bridge32 PORT MAP(
        wb_clk_i => wb_clk_i ,
        wb_rst_i => '0',
        wb_rst_o => wb_rst_i,
        wb_int_i => int_o,
        -- wb_int_o => ,
        wbs_adr_i => m_wb_adr_o ,
        wbs_dat_i => m_wb_dat_o,
        wbs_dat_o => m_wb_dat_i,
        wbs_sel_i => m_wb_sel_o,
        wbs_cyc_i => m_wb_cyc_o,
        wbs_stb_i => m_wb_stb_o,
        wbs_we_i => m_wb_we_o,
        wbs_cti_i => m_wb_cti_o,
        wbs_bte_i => m_wb_bte_o,
        wbs_ack_o => m_wb_ack_i,
        -- wbs_rty_o => ,
        wbs_err_o => m_wb_err_i,
        wbm_adr_o => wbm_adr_o,
        wbm_dat_i => wb_dat_o,
        wbm_dat_o => wb_dat_i,
        wbm_sel_o => wb_sel_i,
        wbm_cyc_o => wb_cyc_i,
        wbm_stb_o => wb_stb_i,
        wbm_we_o => wb_we_i,
        -- wbm_cti_o => ,
        -- wbm_bte_o => ,
        wbm_ack_i => wb_ack_o ,
        wbm_rty_i => '0',
        wbm_err_i => wb_err_o,
        pci_clk_i => PCI_CLOCK,
        pci_rst_i => PCI_RSTn,
        pci_rst_o => pci_rst_o ,
        pci_rst_oe_o => pci_rst_oe_o,
        pci_inta_i => PCI_INTAn,
        pci_inta_o => pci_inta_o,
        pci_inta_oe_o => pci_inta_oe_o,
        pci_req_o => pci_req_o,
        pci_req_oe_o => pci_req_oe_o,
        pci_gnt_i => PCI_GNTn,
        pci_frame_i => PCI_FRAMEn,
        pci_frame_o => pci_frame_o,
        pci_frame_oe_o => pci_frame_oe_o,
        pci_irdy_oe_o => pci_irdy_oe_o,
        pci_devsel_oe_o => pci_devsel_oe_o,
        pci_trdy_oe_o => pci_trdy_oe_o,
        pci_stop_oe_o => pci_stop_oe_o,
        pci_ad_oe_o => pci_ad_oe_o,
        pci_cbe_oe_o => pci_cbe_oe_o,
        pci_irdy_i => PCI_IRDYn,
        pci_irdy_o => pci_irdy_o,
        pci_idsel_i => PCI_IDSEL,
        pci_devsel_i => PCI_DEVSELn,
        pci_devsel_o => pci_devsel_o,
        pci_trdy_i => PCI_TRDYn,
        pci_trdy_o => pci_trdy_o,
        pci_stop_i => PCI_STOPn,
        pci_stop_o => pci_stop_o,
        pci_ad_i => PCI_AD,
        pci_ad_o => pci_ad_o,
        pci_cbe_i => PCI_CBEn,
        pci_cbe_o => pci_cbe_o,
        pci_par_i => PCI_PAR,
        pci_par_o => pci_par_o,
        pci_par_oe_o => pci_par_oe_o,
        pci_perr_i => PCI_PERRn,
        pci_perr_o => pci_perr_o,
        pci_perr_oe_o => pci_perr_oe_o,
        pci_serr_o => pci_serr_o,
        pci_serr_oe_o =>  pci_serr_oe_o
);

Inst_eth_top: eth_top PORT MAP(
        wb_clk_i   => wb_clk_i  ,
        wb_rst_i   => wb_rst_i  ,
        wb_dat_i   => wb_dat_i  ,
        wb_dat_o   => wb_dat_o  ,
        wb_adr_i   => wb_adr_i  ,
        wb_sel_i   => wb_sel_i  ,
        wb_we_i    => wb_we_i   ,
        wb_cyc_i   => wb_cyc_i  ,
        wb_stb_i   => wb_stb_i,
        wb_ack_o   => wb_ack_o  ,
        wb_err_o   => wb_err_o  ,
        m_wb_adr_o => m_wb_adr_o,
        m_wb_sel_o => m_wb_sel_o,
        m_wb_we_o  => m_wb_we_o ,
        m_wb_dat_o => m_wb_dat_o,
        m_wb_dat_i => m_wb_dat_i,
        m_wb_cyc_o => m_wb_cyc_o,
        m_wb_stb_o => m_wb_stb_o,
        m_wb_ack_i => m_wb_ack_i,
        m_wb_err_i => m_wb_err_i,
        mtx_clk_pad_i => MTX_CLK_PAD_I,
        mtxd_pad_o => MTXD_PAD_O,
        mtxen_pad_o => MTXEN_PAD_O,
        mtxerr_pad_o => LED_2,
        mrx_clk_pad_i => MRX_CLK_PAD_I,
        mrxd_pad_i => MRXD_PAD_I,
        mrxdv_pad_i => MRXDV_PAD_I,
        mrxerr_pad_i => MRXERR_PAD_I,
        mcoll_pad_i => MCOLL_PAD_I,
        mcrs_pad_i => MCRS_PAD_I,
        mdc_pad_o => MDC_PAD_O,
        md_pad_i => MD_PAD_IO,
        md_pad_o => md_pad_o,
        md_padoe_o => md_padoe_o,
        m_wb_cti_o => m_wb_cti_o,
        m_wb_bte_o => m_wb_bte_o, 
        int_o => int_o
);

i_icon : icon
port map (
	control0 => control0
	);

i_ila : ila
port map (
	control => control0,
	clk => PCI_CLOCK,
	data => data,
	trig0 => trig0
	);

end architecture ethernet_arch;
Commit	Line	Data
27f6f620	1	LIBRARY ieee;
	2	USE ieee.std_logic_1164.ALL;
	3
	4	entity ethernet is
40a1f26c	5	PORT(
	6	PCI_AD : INOUT std_logic_vector(31 downto 0);
	7	PCI_CLOCK : IN std_logic;
	8	PCI_IDSEL : IN std_logic;
	9	PCI_CBEn : INOUT std_logic_vector (3 downto 0);
	10	PCI_FRAMEn : INOUT std_logic;
	11	PCI_IRDYn : INOUT std_logic;
	12	PCI_RSTn : INOUT std_logic;
	13	PCI_DEVSELn : INOUT std_logic;
	14	PCI_INTAn : INOUT std_logic;
	15	PCI_PERRn : INOUT std_logic;
	16	PCI_SERRn : INOUT std_logic;
	17	PCI_STOPn : INOUT std_logic;
	18	PCI_TRDYn : INOUT std_logic;
	19	PCI_PAR : INOUT std_logic;
	20	PCI_REQn : OUT std_logic;
	21	PCI_GNTn : IN std_logic;
	22
	23	MTX_CLK_PAD_I : IN std_logic;
	24	MTXD_PAD_O : OUT std_logic_vector (3 downto 0);
	25	MTXEN_PAD_O : OUT std_logic;
	26	MRX_CLK_PAD_I : IN std_logic;
	27	MRXD_PAD_I : IN std_logic_vector (3 downto 0);
	28	MRXDV_PAD_I : IN std_logic;
	29	MRXERR_PAD_I : IN std_logic;
	30	MCOLL_PAD_I : IN std_logic;
	31	MCRS_PAD_I : IN std_logic;
	32	MD_PAD_IO : INOUT std_logic;
4d7b5fdd	33	MDC_PAD_O : OUT std_logic;
	34
	35	LED_2 : OUT std_logic
40a1f26c	36	);
27f6f620	37	end ethernet;
40a1f26c	38
27f6f620	39	architecture ethernet_arch of ethernet is
40a1f26c	40
	41	COMPONENT eth_top
	42	PORT(
	43	wb_clk_i : IN std_logic;
	44	wb_rst_i : IN std_logic;
	45	wb_dat_i : IN std_logic_vector(31 downto 0);
	46	wb_adr_i : IN std_logic_vector(11 downto 2);
	47	wb_sel_i : IN std_logic_vector(3 downto 0);
	48	wb_we_i : IN std_logic;
	49	wb_cyc_i : IN std_logic;
	50	wb_stb_i : IN std_logic;
	51	m_wb_dat_i : IN std_logic_vector(31 downto 0);
	52	m_wb_ack_i : IN std_logic;
	53	m_wb_err_i : IN std_logic;
	54	mtx_clk_pad_i : IN std_logic;
	55	mrx_clk_pad_i : IN std_logic;
	56	mrxd_pad_i : IN std_logic_vector(3 downto 0);
	57	mrxdv_pad_i : IN std_logic;
	58	mrxerr_pad_i : IN std_logic;
	59	mcoll_pad_i : IN std_logic;
	60	mcrs_pad_i : IN std_logic;
	61	md_pad_i : IN std_logic;
	62	wb_dat_o : OUT std_logic_vector(31 downto 0);
	63	wb_ack_o : OUT std_logic;
	64	wb_err_o : OUT std_logic;
	65	m_wb_adr_o : OUT std_logic_vector(31 downto 0);
	66	m_wb_sel_o : OUT std_logic_vector(3 downto 0);
	67	m_wb_we_o : OUT std_logic;
	68	m_wb_dat_o : OUT std_logic_vector(31 downto 0);
	69	m_wb_cyc_o : OUT std_logic;
	70	m_wb_stb_o : OUT std_logic;
	71	mtxd_pad_o : OUT std_logic_vector(3 downto 0);
	72	mtxen_pad_o : OUT std_logic;
	73	mtxerr_pad_o : OUT std_logic;
	74	mdc_pad_o : OUT std_logic;
	75	md_pad_o : OUT std_logic;
	76	md_padoe_o : OUT std_logic;
361ec26f	77	m_wb_cti_o : OUT std_logic_vector(2 downto 0);
361ec26f	78	m_wb_bte_o : OUT std_logic_vector(1 downto 0);
40a1f26c	79	int_o : OUT std_logic
	80	);
	81	END COMPONENT;
	82
	83	COMPONENT pci_bridge32
	84	PORT(
	85	wb_clk_i : IN std_logic;
	86	wb_rst_i : IN std_logic;
	87	wb_int_i : IN std_logic;
	88	wbs_adr_i : IN std_logic_vector(31 downto 0);
	89	wbs_dat_i : IN std_logic_vector(31 downto 0);
	90	wbs_sel_i : IN std_logic_vector(3 downto 0);
	91	wbs_cyc_i : IN std_logic;
	92	wbs_stb_i : IN std_logic;
	93	wbs_we_i : IN std_logic;
	94	wbs_cti_i : IN std_logic_vector(2 downto 0);
	95	wbs_bte_i : IN std_logic_vector(1 downto 0);
	96	wbm_dat_i : IN std_logic_vector(31 downto 0);
	97	wbm_ack_i : IN std_logic;
	98	wbm_rty_i : IN std_logic;
	99	wbm_err_i : IN std_logic;
	100	pci_clk_i : IN std_logic;
	101	pci_rst_i : IN std_logic;
	102	pci_inta_i : IN std_logic;
	103	pci_gnt_i : IN std_logic;
	104	pci_frame_i : IN std_logic;
	105	pci_irdy_i : IN std_logic;
	106	pci_idsel_i : IN std_logic;
	107	pci_devsel_i : IN std_logic;
	108	pci_trdy_i : IN std_logic;
	109	pci_stop_i : IN std_logic;
	110	pci_ad_i : IN std_logic_vector(31 downto 0);
	111	pci_cbe_i : IN std_logic_vector(3 downto 0);
	112	pci_par_i : IN std_logic;
	113	pci_perr_i : IN std_logic;
	114	wb_rst_o : OUT std_logic;
	115	wb_int_o : OUT std_logic;
	116	wbs_dat_o : OUT std_logic_vector(31 downto 0);
	117	wbs_ack_o : OUT std_logic;
	118	wbs_rty_o : OUT std_logic;
	119	wbs_err_o : OUT std_logic;
	120	wbm_adr_o : OUT std_logic_vector(31 downto 0);
	121	wbm_dat_o : OUT std_logic_vector(31 downto 0);
	122	wbm_sel_o : OUT std_logic_vector(3 downto 0);
	123	wbm_cyc_o : OUT std_logic;
	124	wbm_stb_o : OUT std_logic;
	125	wbm_we_o : OUT std_logic;
	126	wbm_cti_o : OUT std_logic_vector(2 downto 0);
	127	wbm_bte_o : OUT std_logic_vector(1 downto 0);
	128	pci_rst_o : OUT std_logic;
	129	pci_inta_o : OUT std_logic;
	130	pci_rst_oe_o : OUT std_logic;
	131	pci_inta_oe_o : OUT std_logic;
	132	pci_req_o : OUT std_logic;
	133	pci_req_oe_o : OUT std_logic;
	134	pci_frame_o : OUT std_logic;
	135	pci_frame_oe_o : OUT std_logic;
	136	pci_irdy_oe_o : OUT std_logic;
	137	pci_devsel_oe_o : OUT std_logic;
	138	pci_trdy_oe_o : OUT std_logic;
	139	pci_stop_oe_o : OUT std_logic;
	140	pci_ad_oe_o : OUT std_logic_vector(31 downto 0);
	141	pci_cbe_oe_o : OUT std_logic_vector(3 downto 0);
	142	pci_irdy_o : OUT std_logic;
143	pci_devsel_o : OUT std_logic;
144	pci_trdy_o : OUT std_logic;
145	pci_stop_o : OUT std_logic;
146	pci_ad_o : OUT std_logic_vector(31 downto 0);
147	pci_cbe_o : OUT std_logic_vector(3 downto 0);
148	pci_par_o : OUT std_logic;
149	pci_par_oe_o : OUT std_logic;
150	pci_perr_o : OUT std_logic;
151	pci_perr_oe_o : OUT std_logic;
152	pci_serr_o : OUT std_logic;
153	pci_serr_oe_o : OUT std_logic
154	);
155	END COMPONENT;
156
c8b3e197	157	component icon
	158	port (
	159	control0 : out std_logic_vector(35 downto 0)
70f633de	160	);
c8b3e197	161	end component;
	162
	163	component ila
	164	port (
	165	control : in std_logic_vector(35 downto 0);
	166	clk : in std_logic;
	167	data : in std_logic_vector(63 downto 0);
	168	trig0 : in std_logic_vector(31 downto 0)
	169	);
	170	end component;
70f633de	171
40a1f26c	172	signal pci_rst_o : std_logic;
	173	signal pci_rst_oe_o : std_logic;
	174	signal pci_inta_o : std_logic;
	175	signal pci_inta_oe_o : std_logic;
	176	signal pci_req_o : std_logic;
	177	signal pci_req_oe_o : std_logic;
	178	signal pci_frame_o : std_logic;
	179	signal pci_frame_oe_o : std_logic;
	180	signal pci_irdy_o : std_logic;
	181	signal pci_irdy_oe_o : std_logic;
	182	signal pci_devsel_o : std_logic;
	183	signal pci_devsel_oe_o : std_logic;
	184	signal pci_trdy_o : std_logic;
	185	signal pci_trdy_oe_o : std_logic;
	186	signal pci_stop_o : std_logic;
	187	signal pci_stop_oe_o : std_logic;
	188	signal pci_par_o : std_logic;
	189	signal pci_par_oe_o : std_logic;
	190	signal pci_perr_o : std_logic;
	191	signal pci_perr_oe_o : std_logic;
	192	signal pci_serr_o : std_logic;
	193	signal pci_serr_oe_o : std_logic;
27f6f620	194	signal pci_ad_oe_o : std_logic_vector(31 downto 0);
27f6f620	195	signal pci_cbe_oe_o : std_logic_vector(3 downto 0);
40a1f26c	196	signal pci_ad_o : std_logic_vector (31 downto 0);
	197	signal pci_cbe_o : std_logic_vector (3 downto 0);
	198
27f6f620	199	signal wb_clk_i : std_logic;
	200	signal wb_rst_i : std_logic;
	201	signal wb_dat_i : std_logic_vector (31 downto 0);
	202	signal wb_dat_o : std_logic_vector (31 downto 0);
	203	signal wb_adr_i : std_logic_vector (11 downto 2);
	204	signal wb_sel_i : std_logic_vector (3 downto 0);
	205	signal wb_we_i : std_logic;
	206	signal wb_cyc_i : std_logic;
	207	signal wb_stb_i : std_logic;
	208	signal wb_ack_o : std_logic;
	209	signal wb_err_o : std_logic;
	210	signal m_wb_adr_o : std_logic_vector(31 downto 0);
	211	signal m_wb_sel_o : std_logic_vector(3 downto 0);
	212	signal m_wb_we_o : std_logic;
	213	signal m_wb_dat_o : std_logic_vector(31 downto 0);
	214	signal m_wb_dat_i : std_logic_vector(31 downto 0);
	215	signal m_wb_cyc_o : std_logic;
	216	signal m_wb_stb_o : std_logic;
	217	signal m_wb_ack_i : std_logic;
	218	signal m_wb_err_i : std_logic;
	219	signal md_pad_o : std_logic;
	220	signal md_padoe_o : std_logic;
	221	signal int_o : std_logic;
	222	signal wbm_adr_o : std_logic_vector(31 downto 0);
	223
361ec26f	224	signal m_wb_cti_o : std_logic_vector(2 downto 0);
	225	signal m_wb_bte_o : std_logic_vector(1 downto 0);
	226
c8b3e197	227	signal control0 : std_logic_vector(35 downto 0);
	228	signal data : std_logic_vector(63 downto 0);
	229	signal trig0 : std_logic_vector(31 downto 0);
	230
	231
40a1f26c	232	BEGIN
40a1f26c	233
221bd70b	234	PCI_RSTn <= pci_rst_o when (pci_rst_oe_o = '1') else 'Z';
	235	PCI_INTAn <= pci_inta_o when (pci_inta_oe_o = '1') else 'Z';
	236	PCI_REQn <= pci_req_o when (pci_req_oe_o = '1') else 'Z';
	237	PCI_FRAMEn <= pci_frame_o when (pci_frame_oe_o = '1') else 'Z';
	238	PCI_IRDYn <= pci_irdy_o when (pci_irdy_oe_o = '1') else 'Z';
	239	PCI_DEVSELn <= pci_devsel_o when (pci_devsel_oe_o = '1') else 'Z';
	240	PCI_TRDYn <= pci_trdy_o when (pci_trdy_oe_o = '1') else 'Z';
	241	PCI_STOPn <= pci_stop_o when (pci_stop_oe_o = '1') else 'Z';
27f6f620	242	PCI_PAR <= pci_par_o when (pci_par_oe_o = '1') else 'Z';
221bd70b	243	PCI_PERRn <= pci_perr_o when (pci_perr_oe_o = '1') else 'Z';
221bd70b	244	PCI_SERRn <= pci_serr_o when (pci_serr_oe_o = '1') else 'Z';
27f6f620	245	MD_PAD_IO <= md_pad_o when (md_padoe_o = '1') else 'Z';
	246
	247	BLA1: FOR i in 31 downto 0 generate
	248	PCI_AD(i) <= pci_ad_o(i) when (pci_ad_oe_o(i) = '1') else 'Z';
	249	end generate;
	250
	251	BLA2: FOR i in 3 downto 0 generate
	252	PCI_CBEn(i) <= pci_cbe_o(i) when (pci_cbe_oe_o(i) = '1') else 'Z';
	253	end generate;
	254
3f7aa675	255	wb_adr_i(11 downto 2) <= (others => '0');
3f7aa675	256	wb_adr_i <= wbm_adr_o (7 downto 2);
23944ea1	257
2c4b2f25	258	wb_clk_i <= PCI_CLOCK;
2c4b2f25	259
23944ea1	260	data(31 downto 0) <= wbm_adr_o;
	261	data(40 downto 33) <= wbm_adr_o (7 downto 0);
	262	data(63 downto 41) <= (others => '0');
c8b3e197	263
0d71737f	264	trig0(31 downto 0) <= (
c8b3e197	265	0 => wb_stb_i,
	266	others => '0'
	267	);
	268
40a1f26c	269	Inst_pci_bridge32: pci_bridge32 PORT MAP(
27f6f620	270	wb_clk_i => wb_clk_i ,
	271	wb_rst_i => '0',
	272	wb_rst_o => wb_rst_i,
	273	wb_int_i => int_o,
	274	-- wb_int_o => ,
	275	wbs_adr_i => m_wb_adr_o ,
	276	wbs_dat_i => m_wb_dat_o,
	277	wbs_dat_o => m_wb_dat_i,
	278	wbs_sel_i => m_wb_sel_o,
	279	wbs_cyc_i => m_wb_cyc_o,
	280	wbs_stb_i => m_wb_stb_o,
	281	wbs_we_i => m_wb_we_o,
361ec26f	282	wbs_cti_i => m_wb_cti_o,
361ec26f	283	wbs_bte_i => m_wb_bte_o,
27f6f620	284	wbs_ack_o => m_wb_ack_i,
	285	-- wbs_rty_o => ,
	286	wbs_err_o => m_wb_err_i,
	287	wbm_adr_o => wbm_adr_o,
	288	wbm_dat_i => wb_dat_o,
	289	wbm_dat_o => wb_dat_i,
	290	wbm_sel_o => wb_sel_i,
	291	wbm_cyc_o => wb_cyc_i,
	292	wbm_stb_o => wb_stb_i,
	293	wbm_we_o => wb_we_i,
	294	-- wbm_cti_o => ,
	295	-- wbm_bte_o => ,
	296	wbm_ack_i => wb_ack_o ,
	297	wbm_rty_i => '0',
	298	wbm_err_i => wb_err_o,
40a1f26c	299	pci_clk_i => PCI_CLOCK,
221bd70b	300	pci_rst_i => PCI_RSTn,
40a1f26c	301	pci_rst_o => pci_rst_o ,
40a1f26c	302	pci_rst_oe_o => pci_rst_oe_o,
221bd70b	303	pci_inta_i => PCI_INTAn,
40a1f26c	304	pci_inta_o => pci_inta_o,
	305	pci_inta_oe_o => pci_inta_oe_o,
	306	pci_req_o => pci_req_o,
	307	pci_req_oe_o => pci_req_oe_o,
221bd70b	308	pci_gnt_i => PCI_GNTn,
221bd70b	309	pci_frame_i => PCI_FRAMEn,
40a1f26c	310	pci_frame_o => pci_frame_o,
	311	pci_frame_oe_o => pci_frame_oe_o,
	312	pci_irdy_oe_o => pci_irdy_oe_o,
	313	pci_devsel_oe_o => pci_devsel_oe_o,
	314	pci_trdy_oe_o => pci_trdy_oe_o,
	315	pci_stop_oe_o => pci_stop_oe_o,
	316	pci_ad_oe_o => pci_ad_oe_o,
	317	pci_cbe_oe_o => pci_cbe_oe_o,
221bd70b	318	pci_irdy_i => PCI_IRDYn,
40a1f26c	319	pci_irdy_o => pci_irdy_o,
40a1f26c	320	pci_idsel_i => PCI_IDSEL,
221bd70b	321	pci_devsel_i => PCI_DEVSELn,
40a1f26c	322	pci_devsel_o => pci_devsel_o,
221bd70b	323	pci_trdy_i => PCI_TRDYn,
40a1f26c	324	pci_trdy_o => pci_trdy_o,
221bd70b	325	pci_stop_i => PCI_STOPn,
40a1f26c	326	pci_stop_o => pci_stop_o,
	327	pci_ad_i => PCI_AD,
	328	pci_ad_o => pci_ad_o,
221bd70b	329	pci_cbe_i => PCI_CBEn,
40a1f26c	330	pci_cbe_o => pci_cbe_o,
	331	pci_par_i => PCI_PAR,
	332	pci_par_o => pci_par_o,
	333	pci_par_oe_o => pci_par_oe_o,
221bd70b	334	pci_perr_i => PCI_PERRn,
40a1f26c	335	pci_perr_o => pci_perr_o,
	336	pci_perr_oe_o => pci_perr_oe_o,
	337	pci_serr_o => pci_serr_o,
	338	pci_serr_oe_o => pci_serr_oe_o
	339	);
	340
	341	Inst_eth_top: eth_top PORT MAP(
27f6f620	342	wb_clk_i => wb_clk_i ,
	343	wb_rst_i => wb_rst_i ,
	344	wb_dat_i => wb_dat_i ,
	345	wb_dat_o => wb_dat_o ,
	346	wb_adr_i => wb_adr_i ,
	347	wb_sel_i => wb_sel_i ,
	348	wb_we_i => wb_we_i ,
	349	wb_cyc_i => wb_cyc_i ,
3f7aa675	350	wb_stb_i => wb_stb_i,
27f6f620	351	wb_ack_o => wb_ack_o ,
	352	wb_err_o => wb_err_o ,
	353	m_wb_adr_o => m_wb_adr_o,
	354	m_wb_sel_o => m_wb_sel_o,
	355	m_wb_we_o => m_wb_we_o ,
	356	m_wb_dat_o => m_wb_dat_o,
	357	m_wb_dat_i => m_wb_dat_i,
	358	m_wb_cyc_o => m_wb_cyc_o,
	359	m_wb_stb_o => m_wb_stb_o,
	360	m_wb_ack_i => m_wb_ack_i,
	361	m_wb_err_i => m_wb_err_i,
	362	mtx_clk_pad_i => MTX_CLK_PAD_I,
	363	mtxd_pad_o => MTXD_PAD_O,
	364	mtxen_pad_o => MTXEN_PAD_O,
4d7b5fdd	365	mtxerr_pad_o => LED_2,
27f6f620	366	mrx_clk_pad_i => MRX_CLK_PAD_I,
	367	mrxd_pad_i => MRXD_PAD_I,
	368	mrxdv_pad_i => MRXDV_PAD_I,
	369	mrxerr_pad_i => MRXERR_PAD_I,
	370	mcoll_pad_i => MCOLL_PAD_I,
	371	mcrs_pad_i => MCRS_PAD_I,
	372	mdc_pad_o => MDC_PAD_O,
	373	md_pad_i => MD_PAD_IO,
	374	md_pad_o => md_pad_o,
	375	md_padoe_o => md_padoe_o,
361ec26f	376	m_wb_cti_o => m_wb_cti_o,
361ec26f	377	m_wb_bte_o => m_wb_bte_o,
27f6f620	378	int_o => int_o
40a1f26c	379	);
40a1f26c	380
c8b3e197	381	i_icon : icon
	382	port map (
	383	control0 => control0
	384	);
	385
	386	i_ila : ila
	387	port map (
	388	control => control0,
	389	clk => PCI_CLOCK,
	390	data => data,
	391	trig0 => trig0
	392	);
70f633de	393
27f6f620	394	end architecture ethernet_arch;