Update ChipScope coregeneration to coregen as used in ISE Design Suite 10.1
[raggedstone] / dhwk / ila.xco
CommitLineData
40a64bf1
MG
1# BEGIN Project Options
2SET addpads = False
3SET asysymbol = False
4SET busformat = BusFormatAngleBracketNotRipped
5SET createndf = False
6SET designentry = VHDL
7SET device = xc3s1500
8SET devicefamily = spartan3
9SET flowvendor = Other
10SET formalverification = False
11SET foundationsym = False
12SET implementationfiletype = Ngc
13SET package = fg456
14SET removerpms = False
15SET simulationfiles = Structural
16SET speedgrade = -4
17SET verilogsim = False
18SET vhdlsim = True
19# END Project Options
20# BEGIN Select
21SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.02.a
22# END Select
23# BEGIN Parameters
24CSET component_name=ila
25CSET counter_width_1=Disabled
26CSET counter_width_10=Disabled
27CSET counter_width_11=Disabled
28CSET counter_width_12=Disabled
29CSET counter_width_13=Disabled
30CSET counter_width_14=Disabled
31CSET counter_width_15=Disabled
32CSET counter_width_16=Disabled
33CSET counter_width_2=Disabled
34CSET counter_width_3=Disabled
35CSET counter_width_4=Disabled
36CSET counter_width_5=Disabled
37CSET counter_width_6=Disabled
38CSET counter_width_7=Disabled
39CSET counter_width_8=Disabled
40CSET counter_width_9=Disabled
41CSET data_port_width=96
42CSET data_same_as_trigger=false
43CSET enable_storage_qualification=true
44CSET enable_trigger_output_port=false
45CSET exclude_from_data_storage_1=true
46CSET exclude_from_data_storage_10=true
47CSET exclude_from_data_storage_11=true
48CSET exclude_from_data_storage_12=true
49CSET exclude_from_data_storage_13=true
50CSET exclude_from_data_storage_14=true
51CSET exclude_from_data_storage_15=true
52CSET exclude_from_data_storage_16=true
53CSET exclude_from_data_storage_2=true
54CSET exclude_from_data_storage_3=true
55CSET exclude_from_data_storage_4=true
56CSET exclude_from_data_storage_5=true
57CSET exclude_from_data_storage_6=true
58CSET exclude_from_data_storage_7=true
59CSET exclude_from_data_storage_8=true
60CSET exclude_from_data_storage_9=true
61CSET match_type_1=basic
62CSET match_type_10=basic
63CSET match_type_11=basic
64CSET match_type_12=basic
65CSET match_type_13=basic
66CSET match_type_14=basic
67CSET match_type_15=basic
68CSET match_type_16=basic
69CSET match_type_2=basic
70CSET match_type_3=basic
71CSET match_type_4=basic
72CSET match_type_5=basic
73CSET match_type_6=basic
74CSET match_type_7=basic
75CSET match_type_8=basic
76CSET match_type_9=basic
77CSET match_units_1=1
78CSET match_units_10=1
79CSET match_units_11=1
80CSET match_units_12=1
81CSET match_units_13=1
82CSET match_units_14=1
83CSET match_units_15=1
84CSET match_units_16=1
85CSET match_units_2=1
86CSET match_units_3=1
87CSET match_units_4=1
88CSET match_units_5=1
89CSET match_units_6=1
90CSET match_units_7=1
91CSET match_units_8=1
92CSET match_units_9=1
93CSET max_sequence_levels=1
94CSET number_of_trigger_ports=1
95CSET sample_data_depth=4096
96CSET sample_on=Rising
97CSET trigger_port_width_1=32
98CSET trigger_port_width_10=8
99CSET trigger_port_width_11=8
100CSET trigger_port_width_12=8
101CSET trigger_port_width_13=8
102CSET trigger_port_width_14=8
103CSET trigger_port_width_15=8
104CSET trigger_port_width_16=8
105CSET trigger_port_width_2=8
106CSET trigger_port_width_3=8
107CSET trigger_port_width_4=8
108CSET trigger_port_width_5=8
109CSET trigger_port_width_6=8
110CSET trigger_port_width_7=8
111CSET trigger_port_width_8=8
112CSET trigger_port_width_9=8
113CSET use_rpms=true
114# END Parameters
115GENERATE
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