Update ChipScope coregeneration to coregen as used in ISE Design Suite 10.1
[raggedstone] / dhwk / vio.xco
CommitLineData
40a64bf1
MG
1# BEGIN Project Options
2SET addpads = False
3SET asysymbol = False
4SET busformat = BusFormatAngleBracketNotRipped
5SET createndf = False
6SET designentry = VHDL
7SET device = xc3s1500
8SET devicefamily = spartan3
9SET flowvendor = Other
10SET formalverification = False
11SET foundationsym = False
12SET implementationfiletype = Ngc
13SET package = fg456
14SET removerpms = False
15SET simulationfiles = Structural
16SET speedgrade = -4
17SET verilogsim = False
18SET vhdlsim = True
19# END Project Options
20# BEGIN Select
21SELECT VIO_(ChipScope_Pro_-_Virtual_Input/Output) family Xilinx,_Inc. 1.02.a
22# END Select
23# BEGIN Parameters
24CSET asynchronous_input_port_width=4
25CSET asynchronous_output_port_width=8
26CSET component_name=vio
27CSET enable_asynchronous_input_port=true
28CSET enable_asynchronous_output_port=false
29CSET enable_synchronous_input_port=false
30CSET enable_synchronous_output_port=true
31CSET invert_clock_input=false
32CSET synchronous_input_port_width=8
33CSET synchronous_output_port_width=1
34# END Parameters
35GENERATE
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