more chipscope signals
[raggedstone] / ethernet / ethernet.xst
CommitLineData
e00b64cc 1set -xsthdpdir ./xst
2run
3-ifn ethernet.prj
4-ifmt mixed
5-ofn ethernet
6-ofmt NGC
7-p xc3s1500-fg456-4
8-top ethernet
9-opt_mode Speed
10-opt_level 1
4b4adc0d 11-iuc YES
e00b64cc 12-lso ethernet.lso
13-keep_hierarchy NO
14-glob_opt AllClockNets
15-rtlview Yes
16-read_cores YES
17-write_timing_constraints NO
18-cross_clock_analysis NO
19-hierarchy_separator /
20-bus_delimiter <>
21-case maintain
22-slice_utilization_ratio 100
23-verilog2001 YES
24-fsm_extract YES -fsm_encoding Auto
25-safe_implementation No
26-fsm_style lut
27-ram_extract Yes
28-ram_style Auto
29-rom_extract Yes
30-rom_style Auto
31-mux_extract YES
32-decoder_extract YES
33-priority_extract YES
34-shreg_extract YES
35-shift_extract YES
36-xor_collapse YES
37-resource_sharing YES
38-mult_style auto
39-iobuf YES
40-max_fanout 500
41-bufg 8
42-register_duplication YES
43-equivalent_register_removal YES
44-register_balancing No
45-slice_packing YES
46-optimize_primitives NO
47-use_clock_enable Yes
48-use_sync_set Yes
49-use_sync_reset Yes
50-iob auto
51-slice_utilization_ratio_maxmargin 5
0bd88c9e 52-uc ethernet.xcf
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