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377c0242 1-- J.STELZNER\r
2-- INFORMATIK-3 LABOR\r
3-- 23.08.2006\r
4-- File: CONFIG_WR_0.VHD\r
5\r
6library IEEE;\r
7use IEEE.std_logic_1164.all;\r
8\r
9entity CONFIG_WR_0 is\r
10 port\r
11 (\r
12 ADDR_REG :in std_logic_vector(31 downto 0);\r
13 CF_WR_COM :in std_logic;\r
14 IRDY_REGn :in std_logic;\r
15 TRDYn :in std_logic;\r
16 CONF_WR_04H :out std_logic; \r
17 CONF_WR_10H :out std_logic; \r
18 CONF_WR_3CH :out std_logic\r
19--CONF_WR_40H :out std_logic \r
20 );\r
21end entity CONFIG_WR_0;\r
22\r
23architecture CONFIG_WR_0_DESIGN of CONFIG_WR_0 is\r
24\r
25--\r
26--\r
27--\r
28--\r
29--\r
30-- PCI Configuration Space Header\r
31--\r
32-- \ Bit\r
33-- \\r
34--Address |31 24|23 16|15 8|7 0| \r
35-----------------------------------------------------------------\r
36--00 |Device ID |Vendor ID | \r
37--04 |Status |Command |\r
38--08 |Class Code |Revision ID |\r
39--0C |BIST |Header Type |Latency T. |Cache L.S. |\r
40--10-24 |Base Address Register |\r
41--28 |Cardbus CIS Pointer |\r
42--2C |Subsystem ID |Subsystem Vendor ID |\r
43--30 |Expansion ROM Base Address |\r
44--34 |Reserved |\r
45--38 |Reserved |\r
46--3C |Max_Lat |Min_Gnt |Int_Pin |Int_Line |\r
47--40-FF | |\r
48-----------------------------------------------------------------\r
49\r
50\r
51--PCI Bus Commands \r
52--C/BE[3..0] Command Type\r
53--------------------------------------\r
54-- 0000 Interrupt Acknowledge\r
55-- 0001 Special Cycle\r
56-- 0010 I/O Read\r
57-- 0011 I/O Write\r
58-- 0100 Reserved\r
59-- 0101 Reserved\r
60-- 0110 Memory Read\r
61-- 0111 Memory Write\r
62--\r
63-- 1000 Reserved\r
64-- 1001 Reserved\r
65-- 1010 Configuration Read\r
66-- 1011 Configuration Write\r
67-- 1100 Memory Read Multiple \r
68-- 1101 Dual Address Cycle\r
69-- 1110 Memory Read Line\r
70-- 1111 Memory Write and Invalidate\r
71\r
72\r
73--PCI Byte Enable \r
74--C/BE[3..0] gueltige Datenbits \r
75-------------------------------\r
76-- 0000 AD 31..0\r
77-- 1000 AD 23..0\r
78-- 1100 AD 15..0\r
79-- 1110 AD 7..0\r
80\r
81 constant CMD_INT_ACK :std_logic_vector(3 downto 0) := "0000";\r
82 constant CMD_SP_CYC :std_logic_vector(3 downto 0) := "0001";\r
83 constant CMD_IO_READ :std_logic_vector(3 downto 0) := "0010";\r
84 constant CMD_IO_WRITE :std_logic_vector(3 downto 0) := "0011";\r
85 constant CMD_RES_4 :std_logic_vector(3 downto 0) := "0100";\r
86 constant CMD_RES_5 :std_logic_vector(3 downto 0) := "0101";\r
87 constant CMD_MEM_READ :std_logic_vector(3 downto 0) := "0110";\r
88 constant CMD_MEM_WRITE :std_logic_vector(3 downto 0) := "0111";\r
89 constant CMD_RES_8 :std_logic_vector(3 downto 0) := "1000";\r
90 constant CMD_RES_9 :std_logic_vector(3 downto 0) := "1001";\r
91 constant CMD_CONF_READ :std_logic_vector(3 downto 0) := "1010";\r
92 constant CMD_CONF_WRITE :std_logic_vector(3 downto 0) := "1011";\r
93 constant CMD_MEM_READ_M :std_logic_vector(3 downto 0) := "1100";\r
94 constant CMD_DU_ADR_CYC :std_logic_vector(3 downto 0) := "1101";\r
95 constant CMD_MEN_READ_L :std_logic_vector(3 downto 0) := "1110";\r
96 constant CMD_MEM_WRITE_I :std_logic_vector(3 downto 0) := "1111";\r
97\r
98 signal CONFIG_ADDR :std_logic_vector(7 downto 0); \r
99 signal CONFIG_WRITE :std_logic_vector(3 downto 0); \r
100\r
101\r
102begin\r
103\r
104--*******************************************************************\r
105--******************* PCI Write Configuration Address ***************\r
106--*******************************************************************\r
107\r
108 CONFIG_ADDR(7 downto 0) <= ADDR_REG(7 downto 0);\r
109\r
110\r
111 process (CF_WR_COM,IRDY_REGn,TRDYn,CONFIG_ADDR) \r
112 begin\r
113\r
114 if CF_WR_COM = '1' and IRDY_REGn = '0' and TRDYn = '0' then\r
115\r
116 if CONFIG_ADDR = X"04" then CONFIG_WRITE <= "0001";\r
117 elsif CONFIG_ADDR = X"10" then CONFIG_WRITE <= "0010";\r
118 elsif CONFIG_ADDR = X"3C" then CONFIG_WRITE <= "0100";\r
119-- elsif CONFIG_ADDR = X"40" then CONFIG_WRITE <= "1000";\r
120 else CONFIG_WRITE <= "0000";\r
121 end if;\r
122 else CONFIG_WRITE <= "0000";\r
123 end if;\r
124 end process;\r
125\r
126 CONF_WR_04H <= CONFIG_WRITE(0); \r
127 CONF_WR_10H <= CONFIG_WRITE(1); \r
128 CONF_WR_3CH <= CONFIG_WRITE(2); \r
129--CONF_WR_40H <= CONFIG_WRITE(3); \r
130\r
131end architecture CONFIG_WR_0_DESIGN;\r
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